SN74AHC1G14DCK3 [TI]

具有施密特触发输入的单路 2V 至 5.5V 反相器 | DCK | 5 | -40 to 125;
SN74AHC1G14DCK3
型号: SN74AHC1G14DCK3
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

具有施密特触发输入的单路 2V 至 5.5V 反相器 | DCK | 5 | -40 to 125

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ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢇꢃ  
SCLS321N − MARCH 1996 − REVISED JUNE 2005  
D
D
D
Operating Range of 2 V to 5.5 V  
D
D
8-mA Output Drive at 5 V  
Max t of 10 ns at 5 V  
pd  
Low Power Consumption, 10-µA Max I  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
CC  
DCK PACKAGE  
(TOP VIEW)  
DBV PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
NC  
V
Y
1
2
3
5
1
2
3
5
NC  
A
V
Y
CC  
CC  
1
2
3
5
4
NC  
A
V
Y
CC  
A
4
GND  
4
GND  
GND  
NC – No internal connection  
See mechanical drawings for dimensions.  
description/ordering information  
The SN74AHC1G14 contains one inverter gate. The device performs the Boolean function Y = A.  
The device functions as an independent inverter gate, but because of the Schmitt action, gates may have  
different input threshold levels for positive- (V ) and negative-going (V ) signals.  
T+  
T−  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Reel of 3000  
Reel of 250  
Reel of 3000  
Reel of 250  
Reel or 4000  
SN74AHC1G14DBVR  
SN74AHC1G14DBVT  
SN74AHC1G14DCKR  
SN74AHC1G14DCKT  
SN74AHC1G14DRLR  
SOT (SOT-23) − DBV  
A14_  
−40°C to 85°C  
SOT (SC-70) − DCK  
AF_  
AF_  
SOT (SOT-553) – DRL  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
The actual top-side marking has one additional character that designates the assembly/test site.  
FUNCTION TABLE  
INPUT  
A
OUTPUT  
Y
H
L
L
H
logic diagram (positive logic)  
2
4
A
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢍꢠ  
Copyright 2005, Texas Instruments Incorporated  
ꢜ ꢠ ꢝ ꢜꢕ ꢖꢪ ꢘꢗ ꢛ ꢣꢣ ꢡꢛ ꢙ ꢛ ꢚ ꢠ ꢜ ꢠ ꢙ ꢝ ꢥ  
ꢞꢠ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢇ ꢃ  
ꢀ ꢉꢁ ꢈꢊ ꢋ ꢀꢆ ꢅ ꢌꢉ ꢍꢍꢎꢍ ꢏꢉ ꢈ ꢈꢋ ꢏ ꢉ ꢁꢐ ꢋ ꢏꢍꢋ ꢏ ꢈ ꢄꢍ ꢋ  
SCLS321N − MARCH 1996 − REVISED JUNE 2005  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V  
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V  
+ 0.5 V  
O
CC  
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA  
IK  
I
Output clamp current, I  
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA  
OK  
O O CC  
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA  
Continuous current through V  
O
O
CC  
CC  
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
Package thermal impedance, θ (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W  
JA  
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W  
DRL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142°C/W  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
Storage temperature range, T  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
2. The package thermal impedance is calculated in accordance with JESD 51-7.  
recommended operating conditions (see Note 3)  
MIN  
MAX  
5.5  
UNIT  
V
V
V
V
Supply voltage  
Input voltage  
Output voltage  
2
0
0
CC  
5.5  
V
I
V
CC  
V
O
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 2 V  
−50  
−4  
−8  
50  
4
mA  
= 3.3 V 0.3 V  
= 5 V 0.5 V  
= 2 V  
I
High-level output current  
OH  
mA  
mA  
= 3.3 V 0.3 V  
= 5 V 0.5 V  
I
Low-level output current  
OL  
mA  
8
T
A
Operating free-air temperature  
−40  
85  
°C  
NOTE 3: All unused inputs of the device must be held at V  
or GND to ensure proper device operation. Refer to the TI application report,  
CC  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢇꢃ  
ꢀꢉ ꢁꢈ ꢊ ꢋ ꢀꢆꢅ ꢌꢉ ꢍꢍꢎꢍ ꢏꢉꢈ ꢈ ꢋꢏ ꢉꢁ ꢐꢋꢏ ꢍꢋ ꢏ ꢈ ꢄꢍꢋ  
SCLS321N − MARCH 1996 − REVISED JUNE 2005  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
T
A
= 25°C  
PARAMETER  
TEST CONDITIONS  
V
MIN  
MAX  
UNIT  
CC  
MIN  
1.2  
TYP  
MAX  
2.2  
3 V  
4.5 V  
5.5 V  
3 V  
1.2  
1.75  
2.15  
0.9  
2.2  
3.15  
3.85  
1.9  
V
T+  
1.75  
2.15  
0.9  
3.15  
3.85  
1.9  
Positive-going  
V
input threshold voltage  
V
T−  
4.5 V  
5.5 V  
3 V  
1.35  
1.65  
0.3  
2.75  
3.35  
1.2  
1.35  
1.65  
0.3  
2.75  
3.35  
1.2  
Negative-going  
V
V
input threshold voltage  
V  
T
4.5 V  
5.5 V  
2 V  
0.4  
1.4  
0.4  
1.4  
Hysteresis (V − V  
)
T+ T−  
0.5  
1.6  
0.5  
1.6  
1.9  
2
3
1.9  
3 V  
2.9  
2.9  
I
= −50 mA  
OH  
4.5 V  
3 V  
4.4  
4.5  
4.4  
V
V
V
V
OH  
OL  
I
I
= −4 mA  
= −8 mA  
2.58  
3.94  
2.48  
3.8  
OH  
4.5 V  
2 V  
OH  
0.1  
0.1  
0.1  
0.36  
0.36  
0.1  
1
0.1  
0.1  
0.1  
0.44  
0.44  
1
3 V  
I
= 50 mA  
OL  
4.5 V  
3 V  
I
I
= 4 mA  
= 8 mA  
OL  
4.5 V  
0 V to 5.5 V  
5.5 V  
5 V  
OL  
I
I
V = 5.5 V or GND  
mA  
mA  
pF  
I
I
V = V  
or GND,  
or GND  
I = 0  
O
10  
CC  
I
CC  
C
V = V  
2
10  
10  
i
I
CC  
switching characteristics over recommended operating free-air temperature range,  
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)  
V
CC  
T
A
= 25°C  
TYP  
8.3  
FROM  
(INPUT)  
TO  
(OUTPUT)  
LOAD  
CAPACITANCE  
PARAMETER  
MIN  
MAX  
UNIT  
ns  
MIN  
MAX  
12.8  
12.8  
16.3  
16.3  
t
t
t
t
1
1
1
1
15  
15  
PLH  
PHL  
PLH  
PHL  
A
A
Y
Y
C
C
= 15 pF  
= 50 pF  
L
L
8.3  
10.8  
10.8  
18.5  
18.5  
ns  
switching characteristics over recommended operating free-air temperature range,  
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)  
V
CC  
T
A
= 25°C  
TYP  
5.5  
5.5  
7
FROM  
(INPUT)  
TO  
(OUTPUT)  
LOAD  
CAPACITANCE  
PARAMETER  
MIN  
MAX  
UNIT  
ns  
MIN  
MAX  
8.6  
t
t
t
t
1
1
1
1
10  
10  
12  
12  
PLH  
PHL  
PLH  
PHL  
A
A
Y
Y
C
C
= 15 pF  
= 50 pF  
L
L
8.6  
10.6  
10.6  
ns  
7
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢇ ꢃ  
ꢀ ꢉꢁ ꢈꢊ ꢋ ꢀꢆ ꢅ ꢌꢉ ꢍꢍꢎꢍ ꢏꢉ ꢈ ꢈꢋ ꢏ ꢉ ꢁꢐ ꢋ ꢏꢍꢋ ꢏ ꢈ ꢄꢍ ꢋ  
SCLS321N − MARCH 1996 − REVISED JUNE 2005  
operating characteristics, V  
= 5 V, T = 25°C  
A
CC  
PARAMETER  
Power dissipation capacitance  
TEST CONDITIONS  
TYP  
UNIT  
C
No load,  
f = 1 MHz  
9
pF  
pd  
PARAMETER MEASUREMENT INFORMATION  
V
CC  
Open  
GND  
S1  
R
= 1 kΩ  
L
TEST  
S1  
From Output  
Under Test  
Test  
Point  
From Output  
Under Test  
t
/t  
PLH PHL  
Open  
C
C
L
t
/t  
V
CC  
L
PLZ PZL  
(see Note A)  
(see Note A)  
t
/t  
PHZ PZH  
GND  
Open Drain  
V
CC  
LOAD CIRCUIT FOR  
LOAD CIRCUIT FOR  
TOTEM-POLE OUTPUTS  
3-STATE AND OPEN-DRAIN OUTPUTS  
V
CC  
50% V  
CC  
Timing Input  
0 V  
t
w
t
h
t
su  
V
CC  
V
CC  
50% V  
CC  
50% V  
CC  
Input  
50% V  
CC  
50% V  
CC  
Data Input  
0 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
V
V
CC  
CC  
Output  
Control  
50% V  
CC  
50% V  
CC  
50% V  
CC  
50% V  
t
Input  
CC  
0 V  
0 V  
t
t
t
t
PZL  
PLZ  
PLH  
PHL  
Output  
Waveform 1  
V
OH  
V  
CC  
In-Phase  
Output  
50% V  
50% V  
CC  
50% V  
CC  
CC  
V
S1 at V  
(see Note B)  
V
OL  
+ 0.3 V  
CC  
V
OL  
OL  
t
t
t
PHL  
PLH  
PZH  
PHZ  
Output  
Waveform 2  
S1 at GND  
V
V
OH  
OH  
Out-of-Phase  
Output  
V
OH  
− 0.3 V  
50% V  
CC  
50% V  
50% V  
CC  
CC  
V
0 V  
(see Note B)  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. includes probe and jig capacitance.  
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, Z = 50 , t 3 ns, t 3 ns.  
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.  
E. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Oct-2005  
PACKAGING INFORMATION  
Orderable Device  
SN74AHC1G14DBVR  
SN74AHC1G14DBVRE4  
SN74AHC1G14DBVRG4  
SN74AHC1G14DBVT  
SN74AHC1G14DBVTE4  
SN74AHC1G14DCKR  
SN74AHC1G14DCKRE4  
SN74AHC1G14DCKRG4  
SN74AHC1G14DCKT  
SN74AHC1G14DCKTE4  
SN74AHC1G14DRLR  
SN74AHC1G14DRLRG4  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SOT-23  
DBV  
5
5
5
5
5
5
5
5
5
5
5
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SC70  
DBV  
DBV  
DBV  
DBV  
DCK  
DCK  
DCK  
DCK  
DCK  
DRL  
DRL  
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SC70  
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SC70  
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SC70  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SC70  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOP  
4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOP  
4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
MECHANICAL DATA  
MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002  
DCK (R-PDSO-G5)  
PLASTIC SMALL-OUTLINE PACKAGE  
0,30  
0,15  
M
0,10  
0,65  
5
4
0,13 NOM  
1,40 2,40  
1,10 1,80  
1
3
Gage Plane  
2,15  
1,85  
0,15  
0°–8°  
0,46  
0,26  
Seating Plane  
0,10  
1,10  
0,80  
0,10  
0,00  
4093553-2/D 01/02  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion.  
D. Falls within JEDEC MO-203  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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SN74AHC1G14DCKR

SINGLE SCHMITT-TRIGGER INVERTER GATE
TI

SN74AHC1G14DCKRE4

SINGLE SCHMITT-TRIGGER INVERTER GATE
TI

SN74AHC1G14DCKRG4

SINGLE SCHMITT-TRIGGER INVERTER GATE
TI

SN74AHC1G14DCKT

SINGLE SCHMITT-TRIGGER INVERTER GATE
TI

SN74AHC1G14DCKTE4

SINGLE SCHMITT-TRIGGER INVERTER GATE
TI

SN74AHC1G14DCKTG4

SINGLE SCHMITT-TRIGGER INVERTER GATE
TI

SN74AHC1G14DRLR

SINGLE SCHMITT-TRIGGER INVERTER GATE
TI

SN74AHC1G14DRLRG4

SINGLE SCHMITT-TRIGGER INVERTER GATE
TI

SN74AHC1G14_08

SINGLE SCHMITT-TRIGGER INVERTER GATE
TI

SN74AHC1G14_09

SINGLE SCHMITT-TRIGGER INVERTER GATE
TI

SN74AHC1G32

SINGLE 2-INPUT POSITIVE-OR GATE
TI

SN74AHC1G32-Q1

SINGLE 2-INPUT POSITIVE-OR GATE
TI