SN74AHC1G86-EP_16 [TI]
SINGLE 2-INPUT EXCLUSIVE-OR GATE;
| 型号： | SN74AHC1G86-EP_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SINGLE 2-INPUT EXCLUSIVE-OR GATE 输入元件 |
| 文件： | 总8页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AHC1G86-EP
SINGLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCLS709–FEBRUARY 2008
1
FEATURES
•
•
•
•
Max tpd of 10 ns at 5 V
•
Controlled Baseline
Low Power Consumption, 10 µA Max ICC
±8 mA Output Drive at 5 V
–
–
–
One Assembly Site
One Test Site
Schmitt Trigger Action at All Inputs Makes the
Circuit Tolerant for Slower Input Rise and Fall
Time
One Fabrication Site
•
•
Extended Temperature Performance of –55°C
to 125°C
•
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Enhanced Diminishing Manufacturing Sources
(DMS) Support
•
•
ESD Protection Exceeds JESD 22
•
•
•
Enhanced Product-Change Notification
(1)
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
Qualification Pedigree
Operating Range of 2 V to 5.5 V
1000-V Charged-Device Model (C101)
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DCK PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
A
B
VCC
1
2
3
5
1
2
3
5
A
B
VCC
1
2
3
5
4
A
B
VCC
4
GND
Y
4
GND
Y
Y
GND
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The SN74AHC1G86 is a single 2-input exclusive-OR gate. The device performs the Boolean function Y = A
or Y = AB + AB in positive logic.
B
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the
output.
ORDERING INFORMATION(1)
ORDERABLE PART
TA
PACKAGE(2)
SOT (SC-70) - DCK Reel of 3000
TOP-SIDE MARKING(3)
CGB
NUMBER
–55°C to 125°C
SN74AHC1G86MDCKREP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) The actual top-side marking has one additional character that designates the assembly/test site.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74AHC1G86-EP
SINGLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCLS709–FEBRUARY 2008
FUNCTION TABLE
INPUTS
OUTPUT
Y
A
L
B
L
L
H
H
L
L
H
L
H
H
H
EXCLUSIVE-OR LOGIC
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
EXCLUSIVE OR
= 1
These are five equivalent exclusive-OR symbols valid for an SN74AHC1G86 gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITYELEMENT
=
EVEN-PARITY ELEMENT
2k
ODD-PARITY ELEMENT
2k + 1
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
MAX
UNIT
V
VCC Supply voltage range
7
7
VI
Input voltage range(2)
V
VO
IIK
IOK
IO
Output voltage range(2)
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–20
±20
±25
±50
252
mA
mA
mA
mA
°C/W
°C
Output clamp current
VO < 0 or VO = 0 to VCC
VO = 0 to VCC
VCC or GND
Continuous output current
Continuous current through VCCor GND
Package thermal impedance(3)
Storage temperature range
θJA
DCK package
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN74AHC1G86-EP
SN74AHC1G86-EP
SINGLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCLS709–FEBRUARY 2008
Recommended Operating Conditions(1)
MIN
MAX
UNIT
VCC
Supply voltage
2
1.5
2.1
5.5
V
VCC = 2 V
VCC = 3 V
VCC = 5.5 V
VCC = 2 V
VCC = 3 V
VCC = 5.5 V
VIH
High-level input voltage
V
V
3.85
0.5
0.9
VIL
Low-level input voltage
1.65
5.5
VCC
–50
–4
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 2 V
µA
IOH
High-Level output current
Low-Level output current
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
VCC = 2 V
mA
µA
–8
50
IOL
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
4
mA
8
100
20
Δt/Δv
Input transition rise or fall rate
Operating free-air temperature
ns/V
TA
–55
125
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): SN74AHC1G86-EP
SN74AHC1G86-EP
SINGLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCLS709–FEBRUARY 2008
Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
TA = 25°C
TA = –55°C TO 125°C
PARAMETER
TEST CONDITIONS
VCC
UNIT
MIN
TYP
2
MAX
MIN
1.9
MAX
2 V
3 V
1.9
2.9
IOH = –50 µA
3
2.9
VOH
4.5 V
3 V
4.4
4.5
4.4
V
IOH = –4 mA
IOH = –8 mA
2.58
3.94
2.48
3.8
4.5 V
2 V
0.1
0.1
0.1
0.36
0.36
±0.1
1
0.1
0.1
0.1
0.44
0.44
±1
IOL = 50 µA
3 V
VOL
4.5 V
3 V
V
IOL = 4 mA
IOL = 8 mA
4.5 V
0 V to 5.5 V
5.5 V
5 V
II
VI = 5.5 V or GND
VI = VCC or GND, O = 0
VI = VCC or GND
µA
µA
pF
ICC
Ci
10
4
10
10
Switching Characteristics
over operating free-air temperature range, VCC = 3.3 ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C
TYP MAX
TA = –55°C TO 125°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
MIN
1
MAX
16.5
16.5
ns
ns
tPLH
tPHL
9.5
9.5
14.5
14.5
A or B
Y
CL = 50 pF
1
Switching Characteristics
over operating free-air temperature range, VCC = 5 ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
TA = –55°C TO 125°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
MAX
8.8
MIN
1
MAX
10
tPLH
tPHL
6.3
A or B
Y
CL = 50 pF
ns
6.3
8.8
1
10
Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TYP
18
UNIT
pF
Cpd
Power dissipation capacitance
No load, f = 1 MHz
4
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN74AHC1G86-EP
SN74AHC1G86-EP
SINGLE 2-INPUT EXCLUSIVE-OR GATE
www.ti.com
SCLS709–FEBRUARY 2008
PARAMETER MEASUREMENT INFORMATION
V
CC
S1
Open
GND
R
L
= 1 kΩ
TEST
/t
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
Open
PLH PHL
C
L
C
L
t
/t
V
CC
PLZ PZL
(see Note A)
(see Note A)
/t
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
Timing Input
CC
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
50% V
CC
Input
CC
50% V
50% V
CC
Data Input
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
CC
Input
CC
CC
CC
0 V
0 V
t
t
PZL
PLZ
t
t
t
PLH
PHL
Output
Waveform 1
≈V
V
CC
OH
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
S1 at V
CC
V
+ 0.3 V
OL
V
OL
V
OL
(see Note B)
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
− 0.3 V
50% V
50% V
50% V
CC
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 2008, Texas Instruments Incorporated
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Product Folder Link(s): SN74AHC1G86-EP
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