SN74AHC573DWE4 [TI]

OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS; 八路透明D型锁存器3态输出
SN74AHC573DWE4
型号: SN74AHC573DWE4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
八路透明D型锁存器3态输出

锁存器 输出元件
文件: 总18页 (文件大小:575K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ꢊ ꢆꢋꢄꢌ ꢋ ꢍꢄꢁꢀ ꢎꢄꢍꢏ ꢁꢋ ꢐꢑꢋ ꢒꢎ ꢏ ꢌꢄꢋꢆ ꢅ ꢏ  
SCLS242K − OCTOBER 1995 − REVISED JANUARY 2004  
SN54AHC573 . . . J OR W PACKAGE  
SN74AHC573 . . . DB, DGV, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
Operating Range 2-V to 5.5-V V  
CC  
3-State Outputs Directly Drive Bus Lines  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
13  
12  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
description/ordering information  
The ’AHC573 devices are octal transparent  
D-type latches designed for 2-V to 5.5-V V  
operation.  
CC  
When the latch-enable (LE) input is high, the  
Q outputs follow the data (D) inputs. When LE is  
low, the Q outputs are latched at the logic levels  
of the D inputs.  
GND 10  
11 LE  
SN54AHC573 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low) or the high-impedance state. In  
the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and increased drive  
provide the capability to drive bus lines without  
interface or pullup components.  
3
2
1 20 19  
18  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
OE does not affect the internal operations of the  
latches. Old data can be retained or new data can  
be entered while the outputs are in the  
high-impedance state.  
9 10 11 12 13  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
Tube  
SN74AHC573N  
SN74AHC573N  
Tube  
SN74AHC573DW  
SN74AHC573DWR  
SN74AHC573NSR  
SN74AHC573DBR  
SN74AHC573PW  
SN74AHC573PWR  
SN74AHC573DGVR  
SNJ54AHC573J  
SOIC − DW  
AHC573  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
AHC573  
HA573  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HA573  
Tape and reel  
Tape and reel  
Tube  
TVSOP − DGV  
CDIP − J  
HA573  
SNJ54AHC573J  
SNJ54AHC573W  
SNJ54AHC573FK  
CFP − W  
Tube  
SNJ54AHC573W  
SNJ54AHC573FK  
−55°C to 125°C  
LCCC − FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2004, Texas Instruments Incorporated  
ꢊ ꢗ ꢢ ꢚ ꢙꢥ ꢠꢟ ꢝꢞ ꢟꢙ ꢛꢢ ꢤꢖ ꢜꢗ ꢝ ꢝꢙ ꢬꢔ ꢌꢑ ꢎꢍ ꢭ ꢑꢈꢮꢂ ꢈꢂꢉ ꢜꢤꢤ ꢢꢜ ꢚ ꢜ ꢛꢡ ꢝꢡꢚ ꢞ ꢜ ꢚ ꢡ ꢝꢡ ꢞꢝꢡ ꢥ  
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ  
ꢠ ꢗꢤ ꢡꢞꢞ ꢙ ꢝꢧꢡ ꢚ ꢩꢖ ꢞꢡ ꢗ ꢙꢝꢡ ꢥꢦ ꢊ ꢗ ꢜꢤ ꢤ ꢙ ꢝꢧꢡ ꢚ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢞ ꢉ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢖꢙ ꢗ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢂ ꢇ ꢈꢉ ꢀ ꢁꢇ ꢃ ꢄꢅꢆ ꢂ ꢇꢈ  
ꢊꢆ ꢋꢄ ꢌ ꢋ ꢍ ꢄꢁ ꢀꢎꢄꢍ ꢏꢁ ꢋ ꢐꢑꢋ ꢒ ꢎꢏ ꢌꢄꢋꢆ ꢅꢏꢀ  
ꢓꢔ ꢋ ꢅ ꢈ ꢑꢀꢋꢄꢋ ꢏ ꢊꢕꢋ ꢎ ꢕꢋꢀ  
SCLS242K − OCTOBER 1995 − REVISED JANUARY 2004  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)  
1
OE  
11  
LE  
C1  
1D  
19  
1Q  
2
1D  
To Seven Other Channels  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V  
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V  
+ 0.5 V  
O
CC  
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA  
IK  
I
Output clamp current, I  
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA  
OK  
O O CC  
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA  
Continuous current through V  
O
O
CC  
CC  
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mA  
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W  
JA  
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W  
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W  
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W  
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W  
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
2. The package thermal impedance is calculated in accordance with JESD 51-7.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢊ ꢆꢋꢄꢌ ꢋ ꢍꢄꢁꢀ ꢎꢄꢍꢏ ꢁꢋ ꢐꢑꢋ ꢒꢎ ꢏ ꢌꢄꢋꢆ ꢅ ꢏ  
ꢓ ꢔꢋ ꢅ ꢈ ꢑꢀꢋꢄꢋ ꢏ ꢊ ꢕꢋ ꢎ ꢕꢋ  
SCLS242K − OCTOBER 1995 − REVISED JANUARY 2004  
recommended operating conditions (see Note 3)  
SN54AHC573 SN74AHC573  
UNIT  
MIN  
2
MAX  
MIN  
2
MAX  
V
V
Supply voltage  
5.5  
5.5  
V
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 2 V  
= 3 V  
1.5  
2.1  
3.85  
1.5  
2.1  
3.85  
High-level input voltage  
IH  
= 5.5 V  
= 2 V  
0.5  
0.9  
0.5  
0.9  
= 3 V  
V
IL  
Low-level input voltage  
V
= 5.5 V  
1.65  
5.5  
1.65  
5.5  
V
V
Input voltage  
0
0
0
0
V
V
I
Output voltage  
V
CC  
V
CC  
O
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 2 V  
−50  
−4  
−8  
50  
4
−50  
−4  
−8  
50  
4
mA  
= 3.3 V 0.3 V  
= 5 V 0.5 V  
= 2 V  
I
High-level output current  
Low-level output current  
OH  
mA  
mA  
= 3.3 V 0.3 V  
= 5 V 0.5 V  
= 3.3 V 0.3 V  
= 5 V 0.5 V  
I
OL  
mA  
8
8
100  
20  
125  
100  
20  
85  
t/∆v  
Input transition rise or fall rate  
Operating free-air temperature  
ns/V  
T
−55  
−40  
°C  
A
NOTE 3: All unused inputs of the device must be held at V  
or GND to ensure proper device operation. Refer to the TI application report,  
CC  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
T
A
= 25°C  
TYP  
2
SN54AHC573 SN74AHC573  
PARAMETER  
TEST CONDITIONS  
V
UNIT  
CC  
MIN  
1.9  
MAX  
MIN  
1.9  
MAX  
MIN  
1.9  
MAX  
2 V  
3 V  
2.9  
3
2.9  
2.9  
I
= −50 mA  
OH  
4.5 V  
3 V  
4.4  
4.5  
4.4  
4.4  
V
V
OH  
OL  
2.58  
2.48  
2.48  
I
I
= −4 mA  
= −8 mA  
OH  
4.5 V  
2 V  
3.94  
3.8  
3.8  
OH  
0.1  
0.1  
0.1  
0.1  
0.1  
0.5  
0.1  
0.1  
3 V  
I
= 50 mA  
OL  
4.5 V  
3 V  
0.1  
0.1  
V
V
0.36  
0.44  
I
I
= 4 mA  
= 8 mA  
OL  
4.5 V  
0 V to 5.5 V  
5.5 V  
0.36  
0.1  
0.25  
4
0.5  
1*  
0.44  
1
OL  
I
I
I
V = 5.5 V or GND  
mA  
mA  
mA  
pF  
pF  
I
I
V = V or V , V = V  
or GND  
I = 0  
O
2.5  
40  
2.5  
40  
10  
OZ  
CC  
I
IL  
IH  
O
CC  
V = V  
or GND,  
or GND  
5.5 V  
I
CC  
CC  
C
C
V = V  
5 V  
2.5  
3.5  
10  
i
I
V
= V  
O CC  
or GND  
5 V  
o
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V  
= 0 V.  
CC  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢂ ꢇ ꢈꢉ ꢀ ꢁꢇ ꢃ ꢄꢅꢆ ꢂ ꢇꢈ  
ꢊꢆ ꢋꢄ ꢌ ꢋ ꢍ ꢄꢁ ꢀꢎꢄꢍ ꢏꢁ ꢋ ꢐꢑꢋ ꢒ ꢎꢏ ꢌꢄꢋꢆ ꢅꢏꢀ  
ꢓꢔ ꢋ ꢅ ꢈ ꢑꢀꢋꢄꢋ ꢏ ꢊꢕꢋ ꢎ ꢕꢋꢀ  
SCLS242K − OCTOBER 1995 − REVISED JANUARY 2004  
timing requirements over recommended operating free-air temperature range,  
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)  
V
CC  
T
= 25°C  
SN54AHC573 SN74AHC573  
A
UNIT  
MIN  
5
MAX  
MIN  
5
MAX  
MIN  
5
MAX  
t
w
t
su  
t
h
Pulse duration, LE high  
Setup time, data before LE↓  
Hold time, data after LE↓  
ns  
ns  
ns  
3.5  
1.5  
3.5  
1.5  
3.5  
1.5  
timing requirements over recommended operating free-air temperature range,  
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)  
CC  
T
= 25°C  
SN54AHC573 SN74AHC573  
A
UNIT  
MIN  
5
MAX  
MIN  
5
MAX  
MIN  
5
MAX  
t
w
t
su  
t
h
Pulse duration, LE high  
Setup time, data before LE↓  
Hold time, data after LE↓  
ns  
ns  
ns  
3.5  
1.5  
3.5  
1.5  
3.5  
1.5  
switching characteristics over recommended operating free-air temperature range,  
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)  
CC  
T
A
= 25°C  
TYP  
7*  
SN54AHC573 SN74AHC573  
FROM  
(INPUT)  
TO  
(OUTPUT)  
LOAD  
CAPACITANCE  
PARAMETER  
UNIT  
ns  
MIN  
MAX  
11*  
MIN  
1*  
MAX  
13*  
13*  
14*  
14*  
MIN  
1
MAX  
13  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PLH  
PHL  
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
PLH  
PHL  
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
D
Q
Q
Q
Q
Q
Q
Q
Q
C
C
C
C
C
C
C
= 15 pF  
= 15 pF  
= 15 pF  
= 15 pF  
= 50 pF  
= 50 pF  
= 50 pF  
L
L
L
L
L
L
L
7*  
11*  
1*  
1
13  
7.6* 11.9*  
7.6* 11.9*  
7.3* 11.5*  
7.3* 11.5*  
1*  
1
14  
LE  
OE  
OE  
D
ns  
1*  
1
14  
1* 13.5*  
1* 13.5*  
1
13.5  
13.5  
13  
ns  
1
8.3*  
8.3*  
9.5  
11*  
11*  
1*  
1*  
1
13*  
13*  
1
ns  
1
13  
14.5  
14.5  
15.4  
15.4  
15  
16.5  
16.5  
17.5  
17.5  
17  
1
16.5  
16.5  
17.5  
17.5  
17  
ns  
9.5  
1
1
10.1  
10.1  
9.8  
1
1
LE  
OE  
OE  
ns  
1
1
1
1
ns  
9.8  
15  
1
17  
1
17  
10.7  
10.7  
14.5  
14.5  
1.5**  
1
16.5  
16.5  
1
16.5  
16.5  
1.5  
C
C
= 50 pF  
= 50 pF  
ns  
ns  
L
L
1
1
t
sk(o)  
∗∗  
On products compliant to MIL-PRF-38535, this parameter is not production tested.  
On products compliant to MIL-PRF-38535, this parameter does not apply.  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢊ ꢆꢋꢄꢌ ꢋ ꢍꢄꢁꢀ ꢎꢄꢍꢏ ꢁꢋ ꢐꢑꢋ ꢒꢎ ꢏ ꢌꢄꢋꢆ ꢅ ꢏ  
ꢓ ꢔꢋ ꢅ ꢈ ꢑꢀꢋꢄꢋ ꢏ ꢊ ꢕꢋ ꢎ ꢕꢋ  
SCLS242K − OCTOBER 1995 − REVISED JANUARY 2004  
switching characteristics over recommended operating free-air temperature range,  
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)  
CC  
T
A
= 25°C  
TYP  
4.5*  
4.5*  
5*  
SN54AHC573 SN74AHC573  
FROM  
(INPUT)  
TO  
(OUTPUT)  
LOAD  
CAPACITANCE  
PARAMETER  
UNIT  
ns  
MIN  
MAX  
6.8*  
6.8*  
7.7*  
7.7*  
7.7*  
7.7*  
7.7*  
7.7*  
8.8  
MIN  
1
MAX  
8*  
MIN  
1
MAX  
8
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PLH  
PHL  
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
PLH  
PHL  
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
D
Q
Q
Q
Q
Q
Q
Q
Q
C
C
C
C
C
C
C
= 15 pF  
= 15 pF  
= 15 pF  
= 15 pF  
= 50 pF  
= 50 pF  
= 50 pF  
L
L
L
L
L
L
L
1
8*  
1
8
1
9*  
1
9
LE  
OE  
OE  
D
ns  
5*  
1
9*  
1
9
5.2*  
5.2*  
5.2*  
5.2*  
6
1
9*  
1
9
ns  
1
9*  
1
9
1
9*  
1
9
ns  
1
9*  
1
9
1
10  
10  
11  
11  
11  
11  
11  
11  
1
10  
10  
11  
11  
11  
11  
11  
11  
1
ns  
6
8.8  
1
1
6.5  
6.5  
6.7  
6.7  
6.7  
6.7  
9.7  
1
1
LE  
OE  
OE  
ns  
9.7  
1
1
9.7  
1
1
ns  
9.7  
1
1
9.7  
1
1
C
C
= 50 pF  
= 50 pF  
ns  
ns  
L
L
9.7  
1
1
t
1**  
sk(o)  
∗∗  
On products compliant to MIL-PRF-38535, this parameter is not production tested.  
On products compliant to MIL-PRF-38535, this parameter does not apply.  
noise characteristics, V  
= 5 V, C = 50 pF, T = 25°C (see Note 4)  
CC  
L
A
SN74AHC573  
PARAMETER  
UNIT  
MIN  
MAX  
1
V
V
V
V
V
Quiet output, maximum dynamic V  
Quiet output, minimum dynamic V  
V
V
V
V
V
OL(P)  
OL(V)  
OH(V)  
IH(D)  
IL(D)  
OL  
−0.8  
OL  
Quiet output, minimum dynamic V  
High-level dynamic input voltage  
Low-level dynamic input voltage  
4
OH  
3.5  
1.5  
NOTE 4: Characteristics are for surface-mount packages only.  
operating characteristics, V  
= 5 V, T = 25°C  
A
CC  
PARAMETER  
TEST CONDITIONS  
No load, f = 1 MHz  
TYP  
UNIT  
C
Power dissipation capacitance  
16  
pF  
pd  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢂ ꢇ ꢈꢉ ꢀ ꢁꢇ ꢃ ꢄꢅꢆ ꢂ ꢇꢈ  
ꢊꢆ ꢋꢄ ꢌ ꢋ ꢍ ꢄꢁ ꢀꢎꢄꢍ ꢏꢁ ꢋ ꢐꢑꢋ ꢒ ꢎꢏ ꢌꢄꢋꢆ ꢅꢏꢀ  
ꢓꢔ ꢋ ꢅ ꢈ ꢑꢀꢋꢄꢋ ꢏ ꢊꢕꢋ ꢎ ꢕꢋꢀ  
SCLS242K − OCTOBER 1995 − REVISED JANUARY 2004  
PARAMETER MEASUREMENT INFORMATION  
V
CC  
Open  
GND  
S1  
R
= 1 kΩ  
L
TEST  
S1  
From Output  
Under Test  
Test  
Point  
From Output  
Under Test  
t
t
/t  
Open  
PLH PHL  
/t  
C
C
L
t
V
CC  
L
PLZ PZL  
/t  
(see Note A)  
(see Note A)  
GND  
PHZ PZH  
Open Drain  
V
CC  
LOAD CIRCUIT FOR  
LOAD CIRCUIT FOR  
TOTEM-POLE OUTPUTS  
3-STATE AND OPEN-DRAIN OUTPUTS  
V
CC  
50% V  
CC  
Timing Input  
0 V  
t
w
t
h
t
su  
V
CC  
V
CC  
50% V  
CC  
50% V  
CC  
Input  
50% V  
CC  
50% V  
CC  
Data Input  
0 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
V
V
CC  
CC  
Output  
Control  
50% V  
CC  
50% V  
CC  
50% V  
CC  
50% V  
t
Input  
CC  
0 V  
0 V  
t
PZL  
t
t
t
PLZ  
PLH  
PHL  
Output  
Waveform 1  
V
OH  
V  
CC  
In-Phase  
Output  
50% V  
50% V  
CC  
50% V  
CC  
CC  
V
S1 at V  
(see Note B)  
V
OL  
+ 0.3 V  
CC  
V
OL  
OL  
t
t
t
PHL  
PLH  
PZH  
PHZ  
Output  
Waveform 2  
S1 at GND  
V
V
OH  
OH  
Out-of-Phase  
Output  
V
OH  
− 0.3 V  
50% V  
CC  
50% V  
50% V  
CC  
CC  
V
0 V  
(see Note B)  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. includes probe and jig capacitance.  
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, Z = 50 , t 3 ns, t 3 ns.  
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.  
E. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
26-Sep-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
LCCC  
CDIP  
CFP  
Drawing  
5962-9685601Q2A  
5962-9685601QRA  
5962-9685601QSA  
SN74AHC573DBLE  
SN74AHC573DBR  
ACTIVE  
ACTIVE  
FK  
J
20  
20  
20  
20  
20  
1
1
1
TBD  
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
Call TI  
ACTIVE  
W
OBSOLETE  
ACTIVE  
SSOP  
SSOP  
DB  
DB  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AHC573DBRE4  
SN74AHC573DGVR  
SN74AHC573DGVRE4  
SN74AHC573DW  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SSOP  
TVSOP  
TVSOP  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
DB  
DGV  
DGV  
DW  
DW  
DW  
DW  
N
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AHC573DWE4  
SN74AHC573DWR  
SN74AHC573DWRE4  
SN74AHC573N  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
20  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
SN74AHC573NE4  
SN74AHC573NSR  
SN74AHC573NSRE4  
SN74AHC573PW  
PDIP  
N
20  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
SO  
NS  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
NS  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
TSSOP  
PW  
PW  
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AHC573PWE4  
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AHC573PWLE  
SN74AHC573PWR  
OBSOLETE TSSOP  
PW  
PW  
20  
20  
TBD  
Call TI  
Call TI  
ACTIVE  
TSSOP  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AHC573PWRG4  
ACTIVE  
TSSOP  
PW  
20  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SNJ54AHC573FK  
SNJ54AHC573J  
SNJ54AHC573W  
ACTIVE  
ACTIVE  
ACTIVE  
LCCC  
CDIP  
CFP  
FK  
J
20  
20  
20  
1
1
1
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
W
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
Eco Plan  
26-Sep-2005  
(2)  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
MECHANICAL DATA  
MLCC006B – OCTOBER 1996  
FK (S-CQCC-N**)  
LEADLESS CERAMIC CHIP CARRIER  
28 TERMINAL SHOWN  
A
B
NO. OF  
TERMINALS  
**  
18 17 16 15 14 13 12  
MIN  
MAX  
MIN  
MAX  
0.342  
(8,69)  
0.358  
(9,09)  
0.307  
(7,80)  
0.358  
(9,09)  
19  
20  
11  
10  
9
20  
28  
44  
52  
68  
84  
0.442  
(11,23)  
0.458  
(11,63)  
0.406  
(10,31)  
0.458  
(11,63)  
21  
B SQ  
22  
0.640  
(16,26)  
0.660  
(16,76)  
0.495  
(12,58)  
0.560  
(14,22)  
8
A SQ  
23  
0.739  
(18,78)  
0.761  
(19,32)  
0.495  
(12,58)  
0.560  
(14,22)  
7
24  
25  
6
0.938  
(23,83)  
0.962  
(24,43)  
0.850  
(21,6)  
0.858  
(21,8)  
5
1.141  
(28,99)  
1.165  
(29,59)  
1.047  
(26,6)  
1.063  
(27,0)  
26 27 28  
1
2
3
4
0.080 (2,03)  
0.064 (1,63)  
0.020 (0,51)  
0.010 (0,25)  
0.020 (0,51)  
0.010 (0,25)  
0.055 (1,40)  
0.045 (1,14)  
0.045 (1,14)  
0.035 (0,89)  
0.045 (1,14)  
0.035 (0,89)  
0.028 (0,71)  
0.022 (0,54)  
0.050 (1,27)  
4040140/D 10/96  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. This package can be hermetically sealed with a metal lid.  
D. The terminals are gold plated.  
E. Falls within JEDEC MS-004  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000  
DGV (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
24 PINS SHOWN  
0,23  
0,13  
M
0,07  
0,40  
24  
13  
0,16 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
0°ā8°  
0,75  
1
12  
0,50  
A
Seating Plane  
0,08  
0,15  
0,05  
1,20 MAX  
PINS **  
14  
16  
20  
24  
38  
48  
56  
DIM  
A MAX  
A MIN  
3,70  
3,50  
3,70  
3,50  
5,10  
4,90  
5,10  
4,90  
7,90  
7,70  
9,80  
9,60  
11,40  
11,20  
4073251/E 08/00  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.  
D. Falls within JEDEC: 24/48 Pins – MO-153  
14/16/20/56 Pins – MO-194  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001  
DB (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
28 PINS SHOWN  
0,38  
0,22  
0,65  
28  
M
0,15  
15  
0,25  
0,09  
5,60  
5,00  
8,20  
7,40  
Gage Plane  
1
14  
0,25  
A
0°ā8°  
0,95  
0,55  
Seating Plane  
0,10  
2,00 MAX  
0,05 MIN  
PINS **  
14  
16  
20  
24  
28  
30  
38  
DIM  
6,50  
5,90  
6,50  
5,90  
7,50  
8,50  
7,90  
10,50  
9,90  
10,50 12,90  
A MAX  
A MIN  
6,90  
9,90  
12,30  
4040065 /E 12/01  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-150  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process  
in which TI products or services are used. Information published by TI regarding third-party products or services  
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.  
Use of such information may require a license from a third party under the patents or other intellectual property  
of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without  
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction  
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for  
such altered documentation.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that  
product or service voids all express and any implied warranties for the associated TI product or service and  
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.  
Following are URLs where you can obtain information on other Texas Instruments products and application  
solutions:  
Products  
Applications  
Audio  
Amplifiers  
amplifier.ti.com  
www.ti.com/audio  
Data Converters  
dataconverter.ti.com  
Automotive  
www.ti.com/automotive  
DSP  
dsp.ti.com  
Broadband  
Digital Control  
Military  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
Logic  
interface.ti.com  
logic.ti.com  
Power Mgmt  
Microcontrollers  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
Telephony  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address:  
Texas Instruments  
Post Office Box 655303 Dallas, Texas 75265  
Copyright 2005, Texas Instruments Incorporated  

相关型号:

SN74AHC573DWR

OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
TI

SN74AHC573DWRE4

OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
TI

SN74AHC573DWRG4

具有三态输出的八路透明 D 型锁存器 | DW | 20 | -40 to 125
TI

SN74AHC573N

OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
TI

SN74AHC573NE4

OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
TI

SN74AHC573NSR

OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
TI

SN74AHC573NSRE4

OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
TI

SN74AHC573NSRG4

Octal Transparent D-Type Latches With 3-State Outputs 20-SO -40 to 85
TI

SN74AHC573PW

OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
TI

SN74AHC573PWE4

OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
TI

SN74AHC573PWLE

OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
TI

SN74AHC573PWR

OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
TI