SN74AHC594DBRE4 [TI]
8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS; 8位的移位寄存器与输出寄存器
| 型号： | SN74AHC594DBRE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS |
| 文件： | 总17页 (文件大小：441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
SN54AHC594 . . . J OR W PACKAGE
SN74AHC594 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
D
D
Operating Range 2-V to 5.5-V V
CC
8-Bit Serial-In, Parallel-Out Shift
Registers With Storage
Q
Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
D
D
D
D
Independent Direct Overriding Clears
on Shift and Storage Registers
B
Q
C
D
A
Q
SER
Independent Clocks for Shift and
Storage Registers
Q
RCLR
E
Q
12 RCLK
F
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
11
10
9
Q
SRCLK
SRCLR
G
Q
H
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
GND
Q
H′
SN54AHC594 . . . FK PACKAGE
(TOP VIEW)
− 1000-V Charged-Device Model (C101)
description/ordering information
The ’AHC594 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. Separate clocks and direct
overriding clear (SRCLR, RCLR) inputs are
provided on the shift and storage registers. A
3
2
1
20 19
18
SER
RCLR
NC
Q
4
5
6
7
8
D
Q
17
16
E
NC
15 RCLK
14
9 10 11 12 13
Q
F
serial (Q ) output is provided for cascading
H′
SRCLK
Q
G
purposes.
The shift register (SRCLK) and storage register
(RCLK) clocks are positive-edge triggered. If the
clocks are tied together, the shift register always
is one clock pulse ahead of the storage register.
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube
SN74AHC594N
SN74AHC594N
Tube
SN74AHC594D
AHC594
Tape and reel
Tape and reel
Tape and reel
Tube
SN74AHC594DR
SN74AHC594NSR
SN74AHC594DBR
SN74AHC594PW
SN74AHC594PWR
SNJ54AHC594J
SNJ54AHC594W
SNJ54AHC594FK
−40°C to 85°C
SOP − NS
AHC594
HA594
SSOP − DB
TSSOP − PW
HA594
Tape and reel
Tube
CDIP − J
CFP − W
LCCC − FK
SNJ54AHC594J
SNJ54AHC594W
SNJ54AHC594FK
Tube
−55°C to 125°C
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
ꢕ ꢁ ꢗꢑꢀꢀ ꢔ ꢎꢅ ꢑꢐꢓ ꢍꢀ ꢑ ꢁ ꢔꢎꢑꢘ ꢙꢚ ꢛꢜ ꢝꢞꢟ ꢠꢡꢢ ꢣꢙ ꢟꢞ ꢣꢙꢤ ꢛꢣꢜ ꢖꢐ ꢔ ꢘ ꢕ ꢆꢎ ꢍꢔ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢂ ꢇ ꢃꢈ ꢀ ꢁꢉ ꢃ ꢄꢅꢆ ꢂ ꢇꢃ
ꢊꢋ ꢌꢍ ꢎ ꢀꢅ ꢍ ꢏ ꢎ ꢐ ꢑꢒ ꢍꢀ ꢎꢑ ꢐꢀ
ꢓꢍ ꢎ ꢅ ꢔꢕ ꢎ ꢖꢕ ꢎ ꢐꢑ ꢒ ꢍꢀ ꢎꢑ ꢐꢀ
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
FUNCTION TABLE
INPUTS
FUNCTION
SER SRCLK SRCLR RCLK
RCLR
X
X
L
X
X
Shift register is cleared.
First stage of shift register goes low.
Other stages store the data of previous stage, respectively.
L
↑
H
X
X
First stage of shift register goes high.
Other stages store the data of previous stage, respectively.
H
↑
H
X
X
L
X
X
X
↓
X
X
X
H
X
X
X
X
X
↑
↓
X
L
Shift register state is not changed.
Storage register is cleared.
H
H
Shift register data is stored in the storage register.
Storage register state is not changed.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
13
RCLR
12
RCLK
10
SRCLR
11
SRCLK
R
3D
14
15
SER
Q
1D
C1
R
Q
Q
Q
Q
Q
Q
Q
Q
A
B
C
D
C3
R
3D
1
2
2D
C2
R
Q
Q
C3
R
3D
2D
C2
R
C3
R
3D
3
4
5
2D
C2
R
Q
Q
C3
R
3D
2D
C2
R
Q
Q
Q
Q
E
F
C3
R
3D
2D
C2
R
Q
Q
Q
C3
R
3D
6
2D
C2
R
Q
Q
Q
G
C3
R
3D
7
9
Q
Q
2D
C2
R
H
C3
H′
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
3
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ꢊꢋ ꢌꢍ ꢎ ꢀꢅ ꢍ ꢏ ꢎ ꢐ ꢑꢒ ꢍꢀ ꢎꢑ ꢐꢀ
ꢓꢍ ꢎ ꢅ ꢔꢕ ꢎ ꢖꢕ ꢎ ꢐꢑ ꢒ ꢍꢀ ꢎꢑ ꢐꢀ
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
timing diagram
SRCLK
SER
RCLK
SRCLR
RCLR
Q
Q
A
B
Q
Q
C
D
Q
E
Q
F
Q
G
Q
H
Q
H′
4
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SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54AHC594 SN74AHC594
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
2.1
3.85
1.5
2.1
3.85
= 3 V
High-level input voltage
V
V
IH
= 5.5 V
= 2 V
0.5
0.9
0.5
0.9
= 3 V
V
IL
Low-level input voltage
= 5.5 V
1.65
5.5
1.65
5.5
V
V
Input voltage
0
0
0
0
V
V
I
Output voltage
V
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−4
−8
50
4
−50
−4
−8
50
4
mA
= 3.3 V 0.3 V
= 5 V 0.5 V
= 2 V
I
High-level output current
Low-level output current
OH
mA
mA
= 3.3 V 0.3 V
= 5 V 0.5 V
= 3.3 V 0.3 V
= 5 V 0.5 V
I
OL
mA
8
8
100
20
125
100
20
85
Dt/Dv
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
−55
−40
°C
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
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5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢂ ꢇ ꢃꢈ ꢀ ꢁꢉ ꢃ ꢄꢅꢆ ꢂ ꢇꢃ
ꢊꢋ ꢌꢍ ꢎ ꢀꢅ ꢍ ꢏ ꢎ ꢐ ꢑꢒ ꢍꢀ ꢎꢑ ꢐꢀ
ꢓꢍ ꢎ ꢅ ꢔꢕ ꢎ ꢖꢕ ꢎ ꢐꢑ ꢒ ꢍꢀ ꢎꢑ ꢐꢀ
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
2
SN54AHC594 SN74AHC594
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
1.9
MAX
MIN
1.9
MAX
MIN
1.9
MAX
2 V
3 V
2.9
3
2.9
2.9
I
I
= −50 mA
OH
4.5 V
3 V
4.4
4.5
4.4
4.4
V
OH
V
2.58
2.48
2.48
= −4 mA
, I = −4 mA
OH
3.94
3.94
3.8
3.8
3.8
3.8
Q
H′ OH
4.5 V
Q −Q , I
= −8 mA
A
H
OH
2 V
3 V
0.1
0.1
0.1
0.1
0.1
0.5
0.1
0.1
I
I
= 50 mA
OL
4.5 V
3 V
0.1
0.1
V
OL
V
0.36
0.44
= 4 mA
OL
0.36
0.5
0.44
Q
, I
= 4 mA
= 8 mA
V = 5.5 V or GND
H′ OL
4.5 V
0.36
0.1
0.5
1*
0.44
1
Q −Q
I
A
H, OL
I
I
0 V to 5.5 V
5.5 V
mA
mA
pF
I
I
V = V
I
or GND,
or GND
I = 0
O
4
40
40
10
CC
CC
C
V = V
I
5 V
2
10
i
CC
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V
= 0 V.
CC
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
SN54AHC594 SN74AHC594
A
UNIT
MIN
5.5
5
MAX
MIN
5.5
5
MAX
MIN
5.5
5
MAX
RCLK or SRCLK high or low
RCLR or SRCLR low
t
w
Pulse duration
ns
SER before SRCLK↑
3.5
8
3.5
8.5
9
3.5
8.5
9
†
SRCLK↑ before RCLK↑
SRCLR low before RCLK↑
8
Setup time
Hold time
t
t
ns
ns
su
SRCLR high (inactive) before SRCLK↑
RCLR high (inactive) before RCLK↑
SER after SRCLK↑
4.2
4.6
1.5
4.8
5.3
1.5
4.8
5.3
1.5
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
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ꢦ
ꢣ
ꢜ
ꢧ
ꢦ
ꢞ
ꢝ
ꢠ
ꢟ
ꢝ ꢢ ꢜ ꢛ ꢮ ꢣ ꢧꢚ ꢤ ꢜ ꢢ ꢞꢥ ꢝꢢ ꢰ ꢢ ꢩ ꢞꢧ ꢡꢢ ꢣ ꢙꢪ ꢆ ꢚꢤ ꢦꢤ ꢟꢙ ꢢꢦ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢦ
ꢙ
ꢜ
ꢛ
ꢣ
ꢙ
ꢚ
ꢢ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢰ
ꢢ
ꢞ
ꢦ
ꢜ
ꢧ
ꢢ
ꢟ
ꢛ
ꢥ
ꢛ
ꢟ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢜ
ꢤ
ꢦ
ꢢ
ꢝ
ꢢ
ꢜ
ꢛ
ꢮ
ꢣ
ꢮ
ꢞ
ꢤ
ꢩ
ꢜ
ꢪ
ꢎ
ꢢ
ꢫ
ꢤ
ꢜ
ꢍ
ꢣ
ꢜ
ꢙ
ꢦ
ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚ ꢤ ꢣ ꢮꢢ ꢞꢦ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠ ꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢧꢦ ꢞ ꢝꢠꢟ ꢙꢜ ꢬ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢪ
ꢙ
ꢜ
ꢦ
ꢢ
ꢜ
ꢢ
ꢦ
ꢰ
ꢢ
ꢜ
ꢙ
ꢚ
ꢢ
ꢦ
ꢛ
ꢮ
ꢚ
ꢙ
ꢙ
ꢞ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢊ
ꢎ
ꢃ
ꢄ
ꢍ
ꢔ
ꢅ
ꢎ
ꢕ
ꢆ
ꢀ
ꢎ
ꢂ
ꢅ
ꢖ
ꢇ
ꢍ
ꢃ
ꢏ
ꢕ
ꢈ
ꢎ
ꢎ
ꢀ
ꢐ
ꢐ
ꢁ
ꢉ
ꢑ
ꢑ
ꢃ
ꢒ
ꢒ
ꢄ
ꢅ
ꢎ
ꢎ
ꢆ
ꢑ
ꢑ
ꢂ
ꢐ
ꢐ
ꢇ
ꢃ
ꢀ
ꢀ
ꢋ
ꢌ
ꢍꢀ
ꢓ
ꢍ
ꢅ
ꢍꢀ
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
SN54AHC594 SN74AHC594
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
RCLK or SRCLK high or low
RCLR or SRCLR low
t
w
Pulse duration
ns
5.2
3
5.2
3
5.2
3
SER before SRCLK↑
†
SRCLK↑ before RCLK↑
5
5
5
SRCLR low before RCLK↑
5
5
5
Setup time
Hold time
t
t
ns
ns
su
SRCLR high (inactive) before SRCLK↑
RCLR high (inactive) before RCLK↑
SER after SRCLK↑
2.9
3.2
2
3.3
3.7
2
3.3
3.7
2
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
120*
105
SN54AHC594 SN74AHC594
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
80*
55
MAX
MIN
70*
50
1*
MAX
MIN
70
50
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
max
t
t
t
t
t
4.6*
4.9*
5.4*
5.5*
6*
8*
8.2*
9.1*
9.2*
9.8*
8.5*
8.8*
9.7*
9.9*
8.5
8.8
PLH
PHL
PLH
PHL
PHL
C
C
= 15 pF
= 15 pF
RCLK
Q −Q
A
L
L
H
1*
1
1*
1
9.7
ns
SRCLK
Q
H′
1*
1
9.9
C
C
= 15 pF
= 15 pF
1* 10.6*
1
10.6
ns
ns
RCLR
Q −Q
A
L
L
H
t
t
t
t
t
t
5.6*
6.9
8.1
7.7
8.4
9.1
9.2*
10.5
11.9
11.7
12.5
13.1
1*
1
10*
11.1
13.1
12.4
13.9
14.4
1
1
1
1
1
1
10
11.1
13.1
12.4
13.9
14.4
SRCLR
Q
PHL
PLH
PHL
PLH
PHL
PHL
H′
C
C
= 50 pF
= 50 pF
ns
ns
RCLK
Q −Q
A
L
L
H
1
1
SRCLK
Q
H′
1
C
C
= 50 pF
= 50 pF
1
ns
ns
RCLR
Q −Q
A
L
L
H
t
8.5
12.4
1
14
1
14
SRCLR
Q
PHL
H′
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
ꢖ
ꢐ
ꢔ
ꢘ
ꢕ
ꢆ
ꢎ
ꢖ
ꢐ
ꢑ
ꢯ
ꢍ
ꢑ
ꢓ
ꢛ
ꢣ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢦ
ꢣ
ꢜ
ꢧ
ꢦ
ꢞ
ꢝ
ꢠ
ꢝꢢ ꢜ ꢛ ꢮꢣ ꢧꢚ ꢤ ꢜ ꢢ ꢞꢥ ꢝꢢ ꢰ ꢢ ꢩꢞ ꢧꢡꢢ ꢣꢙꢪ ꢆ ꢚꢤ ꢦꢤ ꢟꢙ ꢢꢦ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢦ
ꢟ
ꢙ
ꢜ
ꢛ
ꢣ
ꢙ
ꢚ
ꢢ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢰ
ꢢ
ꢞ
ꢦ
ꢜ
ꢧ
ꢢ
ꢟ
ꢛ
ꢥ
ꢛ
ꢟ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢜ
ꢤ
ꢦ
ꢢ
ꢝ
ꢢ
ꢜ
ꢛ
ꢮ
ꢣ
ꢮ
ꢞ
ꢤ
ꢩ
ꢜ
ꢪ
ꢎ
ꢢ
ꢫ
ꢤ
ꢜ
ꢍ
ꢣ
ꢜ
ꢙ
ꢦ
ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚꢤ ꢣ ꢮꢢ ꢞꢦ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢧꢦ ꢞꢝ ꢠꢟꢙ ꢜ ꢬ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢪ
ꢙ
ꢜ
ꢦ
ꢢ
ꢜ
ꢢ
ꢦ
ꢰ
ꢢꢜ
ꢙ
ꢚ
ꢢ
ꢦ
ꢛ
ꢮ
ꢚ
ꢙ
ꢙ
ꢞ
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢂ ꢇ ꢃꢈ ꢀ ꢁꢉ ꢃ ꢄꢅꢆ ꢂ ꢇꢃ
ꢊꢋ ꢌꢍ ꢎ ꢀꢅ ꢍ ꢏ ꢎ ꢐ ꢑꢒ ꢍꢀ ꢎꢑ ꢐꢀ
ꢓꢍ ꢎ ꢅ ꢔꢕ ꢎ ꢖꢕ ꢎ ꢐꢑ ꢒ ꢍꢀ ꢎꢑ ꢐꢀ
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
170*
140
SN54AHC594 SN74AHC594
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
135*
120
MAX
MIN
115*
95
MAX
MIN
115
95
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
max
t
t
t
t
t
3.3*
6.2*
6.5*
6.8*
7.2*
7.6*
1*
6.5*
6.9*
7.2*
7.6*
8.2*
6.5
6.9
7.2
7.6
8.2
PLH
PHL
PLH
PHL
PHL
C
C
= 15 pF
= 15 pF
RCLK
Q −Q
A
L
L
H
3.7*
1*
1
3.7*
1*
1
ns
SRCLK
Q
H′
4.1*
1*
1
C
C
= 15 pF
= 15 pF
4.5*
1*
1
ns
ns
RCLR
Q −Q
A
L
L
H
t
t
t
t
t
t
4.1*
4.9
5.8
5.5
6
7.1*
7.8
8.9
8.6
9.2
10
1*
1
7.6*
8.3
1
1
1
1
1
1
7.6
8.3
SRCLR
Q
PHL
PLH
PHL
PLH
PHL
PHL
H′
C
C
= 50 pF
= 50 pF
ns
ns
RCLK
Q −Q
A
L
L
H
1
9.7
9.7
1
9.1
9.1
SRCLK
Q
H′
1
10.1
10.7
10.1
10.7
C
C
= 50 pF
= 50 pF
6.6
1
ns
ns
RCLR
Q −Q
A
L
L
H
t
6
9.2
1
10.1
1
10.1
SRCLR
Q
PHL
H′
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
= 5 V, C = 50 pF, T = 25°C (see Note 4)
CC
L
A
SN74AHC594
PARAMETER
UNIT
MIN
TYP
1
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
−0.6
3.8
OL
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
OH
3.5
1.5
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load, f = 1 MHz
112
pF
pd
ꢖ
ꢐ
ꢔ
ꢘ
ꢕ
ꢆ
ꢎ
ꢖ
ꢐ
ꢑ
ꢯ
ꢍ
ꢑ
ꢓ
ꢛ
ꢣ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢦ
ꢣ
ꢜ
ꢧ
ꢦ
ꢞ
ꢝ
ꢠ
ꢟ
ꢝ ꢢ ꢜ ꢛ ꢮ ꢣ ꢧꢚ ꢤ ꢜ ꢢ ꢞꢥ ꢝꢢ ꢰ ꢢ ꢩ ꢞꢧ ꢡꢢ ꢣ ꢙꢪ ꢆ ꢚꢤ ꢦꢤ ꢟꢙ ꢢꢦ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢦ
ꢙ
ꢜ
ꢛ
ꢣ
ꢙ
ꢚ
ꢢ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢰ
ꢢ
ꢞ
ꢦ
ꢜ
ꢧ
ꢢ
ꢟ
ꢛ
ꢥ
ꢛ
ꢟ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢜ
ꢤ
ꢦ
ꢢ
ꢝ
ꢢ
ꢜ
ꢛ
ꢮ
ꢣ
ꢮ
ꢞ
ꢤ
ꢩ
ꢜ
ꢪ
ꢎ
ꢢ
ꢫ
ꢤ
ꢜ
ꢍ
ꢣ
ꢜ
ꢙ
ꢦ
ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚ ꢤ ꢣ ꢮꢢ ꢞꢦ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠ ꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢧꢦ ꢞ ꢝꢠꢟ ꢙꢜ ꢬ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢪ
ꢙ
ꢜ
ꢦ
ꢢ
ꢜ
ꢢ
ꢦ
ꢰ
ꢢ
ꢜ
ꢙ
ꢚ
ꢢ
ꢦ
ꢛ
ꢮ
ꢚ
ꢙ
ꢙ
ꢞ
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢊ
ꢎ
ꢃ
ꢄ
ꢍ
ꢔ
ꢅ
ꢎ
ꢕ
ꢆ
ꢀ
ꢎ
ꢂ
ꢅ
ꢖ
ꢇ
ꢍ
ꢃ
ꢏ
ꢕ
ꢈ
ꢎ
ꢎ
ꢀ
ꢐ
ꢐ
ꢁ
ꢉ
ꢑ
ꢑ
ꢃ
ꢒ
ꢒ
ꢄ
ꢅ
ꢎ
ꢎ
ꢆ
ꢑ
ꢑ
ꢂ
ꢐ
ꢐ
ꢇ
ꢃ
ꢀ
ꢀ
ꢋ
ꢌ
ꢍꢀ
ꢓ
ꢍ
ꢅ
ꢍꢀ
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
CC
50% V
CC
Input
50% V
CC
50% V
CC
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
CC
50% V
CC
50% V
CC
50% V
t
Input
CC
0 V
0 V
t
PZL
t
t
t
PLZ
PLH
PHL
Output
Waveform 1
V
OH
≈V
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
V
OL
+ 0.3 V
CC
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
− 0.3 V
50% V
CC
50% V
50% V
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
9-Aug-2005
PACKAGING INFORMATION
Orderable Device
SN74AHC594D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AHC594DBR
SN74AHC594DBRE4
SN74AHC594DE4
SN74AHC594DR
SSOP
SSOP
SOIC
SOIC
SOIC
PDIP
DB
DB
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AHC594DRE4
SN74AHC594N
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74AHC594NE4
SN74AHC594NSR
SN74AHC594NSRE4
SN74AHC594PW
SN74AHC594PWE4
SN74AHC594PWR
SN74AHC594PWRE4
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SO
NS
NS
PW
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Aug-2005
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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