SN74AHC74DG4 [TI]
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SOIC -40 to 125;
| 型号： | SN74AHC74DG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SOIC -40 to 125 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总27页 (文件大小：1812K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54AHC74, SN74AHC74
www.ti.com
SCLS255K –DECEMBER 1995–REVISED DECEMBER 2013
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
Check for Samples: SN54AHC74, SN74AHC74
1
FEATURES
DESCRIPTION
The ’AHC74 dual positive-edge-triggered devices are
D-type flip-flops.
•
•
Operating Range 2-V to 5.5-V VCC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
A low level at the preset (PRE) or clear (CLR) inputs
sets or resets the outputs, regardless of the levels of
the other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the setup
time requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following
the hold-time interval, data at the D input can be
changed without affecting the levels at the outputs.
•
ESD Protection Exceeds JESD 22
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2013, Texas Instruments Incorporated
SN54AHC74, SN74AHC74
SCLS255K –DECEMBER 1995–REVISED DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. Function Table (Each Flip-Flop)
INPUTS
OUTPUTS
PRE
L
CLR
H
CLK
X
D
X
X
X
H
L
Q
H
Q
L
H
L
X
L
H(1)
H
H(1)
L
L
X
H
H
↑
H
L
H
H
↑
L
H
H
H
L
X
Q0
Q 0
(1) This configuration is unstable; that is, it does not persist when PRE or CLR returns to its inactive (high)
level.
2
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Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHC74 SN74AHC74
SN54AHC74, SN74AHC74
www.ti.com
SCLS255K –DECEMBER 1995–REVISED DECEMBER 2013
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
–0.5 V to 7 V
–0.5 V to 7 V
–0.5 V to VCC + 0.5 V
–20 mA
Supply voltage range, VCC
(
)
(2)
Input voltage range, VI
Output voltage range, VO
(
)
(2)
Input clamp current, IIK (VI < 0)
Output clamp current, IOK (VO < 0 or VO > VCC
)
±20 mA
Continuous output current, IO (VO = 0 to VCC
)
±25 mA
Continuous current through VCC or GND
±50 mA
D package
86°C/W
(3)
DB package
96°C/W
(3)
DGV package
127°C/W
(3)
Package thermal impedance, ΘJA
N package
80°C/W
(3)
NS package
76°C/W
(3)
PW package
113°C/W
(4)
RGY package
47°C/W
Storage temperature range, Tstg
–65°C to 150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
(4) The package thermal impedance is calculated in accordance with JESD 51-5.
Recommended Operating Conditions(1)
SN54AHC74
SN74AHC74
UNIT
MIN
2
MAX
MIN
2
MAX
VCC
Supply voltage
5.5
5.5
V
VCC = 2 V
VCC = 3V
1.5
2.1
3.85
1.5
2.1
3.85
VIH
High-level input voltage
V
V
VCC = 5.5 V
VCC = 2 V
VCC = 3 V
VCC = 5.5 V
0.5
0.9
1.65
5.5
VCC
–50
–4
0.5
0.9
1.65
5.5
VCC
–50
–4
VIL
Low-level input voltage
VI
Input voltage
0
0
0
0
V
V
VO
Output voltage
VCC = 2 V
µA
IOH
High-level output current
Low-level output current
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
VCC = 2 V
mA
µA
–8
–8
50
50
IOL
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
4
4
mA
8
8
100
20
100
20
Δt/Δv
Input transition rise or fall rate
Operating free-air temperature
ns/V
°C
TA
–55
125
–40
125
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 1995–2013, Texas Instruments Incorporated
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SN54AHC74, SN74AHC74
SCLS255K –DECEMBER 1995–REVISED DECEMBER 2013
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
–55°C to 125°C
SN54AHC74
–40°C to 85°C
SN74AHC74
–40°C to 125°C
SN74AHC74
TA = 25°C
PARAMETER
TEST CONDITIONS
VCC
UNIT
MIN
1.9
TYP
2
MAX
MIN
1.9
MAX
MIN
1.9
MAX
MIN
1.9
MAX
2 V
3 V
IOH = -50 mA
2.9
3
2.9
2.9
2.9
VOH
4.5 V
3 V
4.4
4.5
4.4
4.4
4.4
V
IOH = -4 mA
IOH = -8 mA
2.58
3.94
2.48
3.8
2.48
3.8
2.48
3.8
4.5 V
2 V
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.5
0.5
±1
IOL = 50 mA
3 V
VOL
4.5 V
3 V
0.1
0.1
0.1
V
IOL = 4 mA
0.36
0.36
±0.1
0.5
0.44
0.44
±1
IOH = 8 mA
4.5 V
0 V to 5.5 V
0.5
±1(1)
II
VI = 5.5 V or GND
µA
µA
pF
VI = VCC or
IO = 0
ICC
Ci
5.5 V
5 V
2
20
20
10
20
GND,
VI = VCC or GND
2
10
(1) On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
Timing Requirements
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
–40°C to 85°C
SN74AHC74
–40°C to 125°C
SN74AHC74
TA = 25°C
SN54AHC74
UNIT
MIN
6
MAX
MIN
7
MAX
MIN
7
MAX
MIN
7
MAX
PRE or CLR low
CLK
tw
Pulse duration
ns
6
7
7
7
Data
6
7
7
7
tsu
th
Setup time before CLK↑
ns
ns
PRE or CLR inactive
5
5
5
5
Hold time, data after CLK↑
0.5
0.5
0.5
0.5
Timing Requirements
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
–40°C to 85°C
SN74AHC74
–40°C to 125°C
SN74AHC74
TA = 25°C
SN54AHC74
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
PRE or CLR low
CLK
tw
Pulse duration
ns
5
5
5
5
Data
5
5
5
5
tsu
th
Setup time before CLK↑
ns
ns
PRE or CLR inactive
3
3
3
3
Hold time, data after CLK↑
0.5
0.5
0.5
0.5
4
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Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHC74 SN74AHC74
SN54AHC74, SN74AHC74
www.ti.com
SCLS255K –DECEMBER 1995–REVISED DECEMBER 2013
Switching Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.5 V (unless otherwise noted) (see Figure 1)
–40°C to
85°C
SN74AHC74
–40°C to
125°C
SN74AHC74
TA = 25°C
SN54AHC74
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
80(1) 125(1)
TYP
MAX
MIN
70(1)
45
1(1)
1(1)
1(1)
1(1)
1
MAX
MIN MAX
MIN MAX
CL = 15 pF
CL = 50 pF
70
45
70
45
fmax
MHz
ns
50
75
7.6(1)
7.6
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
12.3(1)
12.3
11.9
11.9
15.8
15.8
15.4
15.4
14.5(1)
14.5(1)
14(1)
14(1)
18
1
1
1
1
1
1
1
1
14.5
14.5
14
1
1
1
1
1
1
1
1
14.5
14.5
14
PRE or CLR
CLK
Q or Q
Q or Q
Q or Q
Q or Q
CL = 15 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
6.7
ns
6.7
14
14
10.1
10.1
9.2
18
18
PRE or CLR
CLK
ns
1
18
18
18
1
17.5
17.5
17.5
17.5
17.5
17.5
ns
9.2
1
(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.
Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
–40°C to
85°C
SN74AHC74 SN74AHC74
–40°C to
125°C
TA = 25°C
SN54AHC74
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
130(1) 170(1)
TYP MAX
MIN MAX
110(1)
MIN MAX
MIN MAX
CL = 15 pF
CL = 50 pF
110
75
110
75
fmax
MHz
ns
90
115
75
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
4.8(1) 7.7(1)
4.8(1) 7.7(1)
4.6(1) 7.3(1)
4.6(1) 7.3(1)
1(1)
1(1)
1(1) 8.5(1)
1(1) 8.5(1)
9(1)
9(1)
1
1
1
1
1
1
1
1
9
9
1
1
1
1
1
1
1
1
9
9
PRE or CLR
CLK
Q or Q
Q or Q
Q or Q
Q or Q
CL = 15 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
8.5
8.5
11
8.5
8.5
11
ns
6.3
6.3
6.1
6.1
9.7
9.7
9.3
9.3
1
1
1
1
11
11
PRE or CLR
CLK
ns
11
11
10.5
10.5
10.5
10.5
10.5
10.5
ns
(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.
Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C (see
(1)
)
SN74AHCT74
PARAMETER
UNIT
MIN
MAX
VOL(P)
VOL(V)
VOH(V)
VIH(D)
VIL(D)
Quiet output, maximum dynamic VOL
Quiet output, minimum dynamic VOL
Quiet output, minimum dynamic VOH
High-level dynamic input voltage
Low-level dynamic input voltage
0.8
V
V
V
V
V
–0.8
4.7
3.5
1.5
(1) Characteristics are for surface-mount packages only.
Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
32
UNIT
Cpd
Power dissipation capacitance
pF
Copyright © 1995–2013, Texas Instruments Incorporated
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Product Folder Links: SN54AHC74 SN74AHC74
SN54AHC74, SN74AHC74
SCLS255K –DECEMBER 1995–REVISED DECEMBER 2013
www.ti.com
Figure 1. Load Circuit and Voltage Waveforms
6
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Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHC74 SN74AHC74
SN54AHC74, SN74AHC74
www.ti.com
SCLS255K –DECEMBER 1995–REVISED DECEMBER 2013
REVISION HISTORY
Changes from Revision J (September 2002) to Revision K
Page
•
•
•
•
Updated document to new TI data sheet format. ................................................................................................................. 1
Added ESD warning. ............................................................................................................................................................ 2
Removed Ordering Information table. ................................................................................................................................... 2
Updated operating temperature range. ................................................................................................................................. 3
Copyright © 1995–2013, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
5962-9686001Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
9686001Q2A
SNJ54AHC
74FK
5962-9686001QCA
5962-9686001QDA
SN74AHC74D
ACTIVE
ACTIVE
ACTIVE
CDIP
CFP
J
14
14
14
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-40 to 125
5962-9686001QC
A
SNJ54AHC74J
W
D
5962-9686001QD
A
SNJ54AHC74W
SOIC
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
AHC74
SN74AHC74DBLE
SN74AHC74DBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
14
14
TBD
Call TI
Call TI
-40 to 125
-40 to 125
2000
2000
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
HA74
SN74AHC74DBRG4
SN74AHC74DG4
SN74AHC74DGVR
SN74AHC74DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SOIC
TVSOP
SOIC
SOIC
PDIP
DB
D
14
14
14
14
14
14
14
14
14
14
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
HA74
Green (RoHS
& no Sb/Br)
AHC74
HA74
DGV
D
2000
2500
2500
25
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
AHC74
AHC74
SN74AHC74N
SN74AHC74N
AHC74
HA74
SN74AHC74DRE4
SN74AHC74N
D
Green (RoHS
& no Sb/Br)
N
Pb-Free
(RoHS)
SN74AHC74NE4
SN74AHC74NSR
SN74AHC74PW
SN74AHC74PWG4
PDIP
N
25
Pb-Free
(RoHS)
N / A for Pkg Type
SO
NS
PW
PW
2000
90
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
90
Green (RoHS
& no Sb/Br)
HA74
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
SN74AHC74PWLE
SN74AHC74PWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
14
14
TBD
Call TI
Call TI
-40 to 125
-40 to 125
PW
2000
2000
3000
3000
1
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
HA74
HA74
HA74
HA74
5962-
SN74AHC74PWRG4
SN74AHC74RGYR
SN74AHC74RGYRG4
SNJ54AHC74FK
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
VQFN
VQFN
LCCC
PW
RGY
RGY
FK
14
14
14
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
POST-PLATE
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
-40 to 125
-40 to 125
-40 to 125
-55 to 125
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TBD
9686001Q2A
SNJ54AHC
74FK
SNJ54AHC74J
SNJ54AHC74W
ACTIVE
ACTIVE
CDIP
CFP
J
14
14
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-9686001QC
A
SNJ54AHC74J
W
5962-9686001QD
A
SNJ54AHC74W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54AHC74, SN74AHC74 :
Catalog: SN74AHC74
•
Enhanced Product: SN74AHC74-EP, SN74AHC74-EP
•
Military: SN54AHC74
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Dec-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AHC74DBR
SN74AHC74DGVR
SN74AHC74DR
SSOP
TVSOP
SOIC
DB
DGV
D
14
14
14
14
14
2000
2000
2500
2000
3000
330.0
330.0
330.0
330.0
330.0
16.4
12.4
16.4
12.4
12.4
8.2
6.8
6.6
4.0
2.5
1.6
12.0
8.0
8.0
8.0
8.0
16.0
12.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
6.5
9.0
2.1
SN74AHC74PWR
SN74AHC74RGYR
TSSOP
VQFN
PW
RGY
6.9
5.6
1.6
3.75
3.75
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Dec-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74AHC74DBR
SN74AHC74DGVR
SN74AHC74DR
SSOP
TVSOP
SOIC
DB
DGV
D
14
14
14
14
14
2000
2000
2500
2000
3000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
35.0
38.0
35.0
35.0
SN74AHC74PWR
SN74AHC74RGYR
TSSOP
VQFN
PW
RGY
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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