SN74AHC8541 [TI]
SN74AHC8541;
| 型号： | SN74AHC8541 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SN74AHC8541 |
| 文件： | 总9页 (文件大小：468K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AHC8541
www.ti.com ..................................................................................................................................................................................................... SCLS716–APRIL 2009
8-BIT INVERTING/NON-INVERTING SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS
1
FEATURES
N OR PW PACKAGE
•
•
•
Operating Range of 2 V to 5.5 V VCC
(TOP VIEW)
8-Bit Inverting/Non-Inverting Outputs
V
1
2
20
T/C
D1
CC
20-Pin Thin Shrink Small-Outline Package
[TSSOP (PW)] and 20-Pin Plastic Dual-In-Line
Package [PDIP (N)]
19
18
17
16
15
14
13
12
11
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
OE
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
D8
10
GND
DESCRIPTION
The SN74AHC8541 8-bit inverting/non-inverting buffers are ideal for driving bus lines or buffer memory address
registers. These devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit
board layout.
All outputs are in the high-impedance state (disabled) when the output-enable (OE) input is high. When OE is
low, the respective gate passes the data from the D input to its Y output.
The T/C input selects inverting or non-inverting data transfer. When the T/C input is high, it provides
non-inverting buffers. When the T/C input is low, it provides inverting buffers when they are not in the
high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(EACH BUFFER)(1)
INPUTS
OUTPUT
Y
OE
L
T/C
H
D
H
L
H
L
L
H
L
L
H
L
L
L
L
H
Z
H
X
X
(1) L: Low-level
H: High-level
X: Irrelevant
Z: High-impedance (off)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
SN74AHC8541
SCLS716–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
LOGIC SYMBOL
1
T/C
11
OE
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
D1
D2
D3
D4
D5
D6
D7
D8
1
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
LOGIC DIAGRAM (POSITIVE LOGIC)
1
11
OE
T/C
19
Y1
2
D1
To Seven Other Channels
ABSOLUTE MAXIMUM RATINGS(1)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impendance or power-off state(2)
Output voltage range applied in the high- or low-state(2)(3)
7
7
7
V
V
VO
VCC + 0.5
–20
V
IIK
IOK
IO
Input clamp current
VI < 0 V
V
Output clamp current
VO < 0 V or VO > VCC
VO = 0 V to VCC
±50
mA
mA
mA
Continuous output current
Continuous current through VCC or GND
±25
±50
N package
69
θJA
Thermal impedance(4)
°C/W
°C
PW package
83
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 5.5 V maximum.
(4) The package thermal impendance is calculatead in accordance with JESD 51-7.
2
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN74AHC8541
SN74AHC8541
www.ti.com ..................................................................................................................................................................................................... SCLS716–APRIL 2009
RECOMMENDED OPERATING CONDITIONS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
2
MAX
UNIT
VCC
Supply voltage
5.5
V
VCC = 2 V
1.5
VIH
High-level input voltage
VCC = 3.3 V ±0.3 V
VCC = 5 V ±0.5 V
VCC = 2 V
VCC × 0.7
VCC × 0.7
V
V
0.5
VIL
Low-level input voltage
VCC = 3.3 V ±0.3 V
VCC = 5 V ±0.5 V
VCC × 0.3
VCC × 0.3
5.5
VCC
5.5
–50
–6
VI
Input voltage
0
0
0
V
High or low state
3-state
VO
Output voltage
V
VCC = 2 V
µA
mA
µA
mA
IOH
High-level output current
Low-level output current
VCC = 3.3 V ±0.3 V
VCC = 5 V ±0.5 V
VCC = 2 V
–12
50
IOL
VCC = 3.3 V ±0.3 V
VCC = 5 V ±0.5 V
VCC = 3.3 V ±0.3 V
VCC = 5 V ±0.5 V
VCC = 3.3 V ±0.3 V
VCC = 5 V ±0.5 V
VCC = 3.3 V ±0.3 V
VCC = 5 V ±0.5 V
6
12
0
0
100
20
T/C, OE
ns/V
Input transition rise or
fall rate
Δt/ΔV
0
3
D
ms/V
0
2
100
60
–40
tpa
TA
Pulse reception time(2)
ns
°C
Operating free-air temperature
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
(2) Buffer inputs D1 to D8 might accept no pulse after tpa period after receiving the first pulse edge. If the input state changes from H to L or
L to H in this period, the corresponding output changes from L to H or H to L respectively, in tpa + tpd as delay time in worst-case
scenario.
Maximum input frequency, fmax, is calculated by the following formula:
fmax = input pulse duty cycle/(tpa(min) + tpd(max)) when input pulse duty cycle <50%
fmax = (1 – input pulse duty cycle)/(tpa(min) + tpd(max)) when input pulse duty cycle >50%
Copyright © 2009, Texas Instruments Incorporated
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SN74AHC8541
SCLS716–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
3.3 V
5 V
MIN
TYP(1)
MAX
2.31
3.5
UNIT
Positive-going input threshold
voltage
VT+
VT–
ΔVT
D
D
D
V
3.3 V
5 V
0.99
1.5
Negative-going input
threshold voltage
V
V
3.3 V
5 V
0.33
0.5
1.32
2
Hysteresis (VT+ – VT–
)
IOH = –50 µA
2 V
1.9
VOH
High-level output voltage
Low-level output voltage
IOH = –6 µA
3 V
2.48
3.8
V
V
IOH = –12 µA
4.5 V
2 V
IOL = 50 µA
0.1
0.44
0.55
±1
VOL
IOL = 6 µA
3 V
IOL = 12 µA
4.5 V
0 V to 5.5 V
5.5 V
5.5 V
5 V
II
Input current
VI = 5.5 V or GND
VO = VCC or GND
VI = VCC or GND, IO = 0 A
VI = VCC or GND
VO = VCC or GND
µA
µA
µA
pF
pF
pF
IOZ
ICC
CI
OFF-state output current
Supply current
±5
20
Input capacitance
Output capacitance
3
5
CO
Cpd
5 V
Power disspation capacitance f = 1 MHz, no load
5 V
15
(1) All typical values are at TA = 25°C.
SWITCHING CHARACTERISTICS
VCC = 3.3 V ±0.3 V, TA = –40°C to 85°C, see Figure 1
FROM
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
(INPUT)
MIN
TYP
MAX UNIT
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
1
1
1
1
1
1
1
1
15
18
16
20
9
29
D
34
ns
30
tpd
Propagation delay time
Y
T/C
OE
OE
36
16
ns
20
ten
Enable time
Disable time
Y
Y
11
8
14
ns
18
tdis
11
SWITCHING CHARACTERISTICS
VCC = 5 V ±0.5 V, TA = –40°C to 85°C, see Figure 1
FROM
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
(INPUT)
MIN
TYP
MAX UNIT
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
1
1
1
1
1
1
1
1
10
12
11
13
6
16
D
20
ns
17
tpd
Propagation delay time
Y
T/C
OE
OE
21
10.5
ns
ten
Enable time
Disable time
Y
Y
8
12.5
6
10
ns
tdis
8
11.5
4
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): SN74AHC8541
SN74AHC8541
www.ti.com ..................................................................................................................................................................................................... SCLS716–APRIL 2009
NOISE CHARACTERISTICS(1)
VCC = 5 V, CL = 50 pF, TA = –40°C to 85°C
PARAMETER
Quiet output, maximum dynamic VOL
Quiet output, minimum dynamic VOL
Quiet output, minimum dynamic VOH
High-level dynamic input voltage
Low--level dynamic input voltage
MIN
TYP
0.4
MAX
UNIT
VOL(P)
VOL(V)
VOH(V)
VIH(D)
VIL(D)
V
V
V
V
V
–0.4
4.5
3.5
1.5
(1) Characteristics are for surface-mount packages only.
PARAMETER MEASUREMENT INFORMATION
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output
control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf
≤3 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPZL and tPZH are the same as ten
F. tPLZ and tPHZ are the same as tdis
G. tPLH and tPHL are the same as tpd
.
.
.
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 2009, Texas Instruments Incorporated
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5
Product Folder Link(s): SN74AHC8541
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74AHC8541N
ACTIVE
PDIP
N
20
20
RoHS &
NIPDAU
N / A for Pkg Type
-40 to 85
SN74AHC8541N
Non-Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
PDIP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
SN74AHC8541N
N
20
20
506
13.97
11230
4.32
Pack Materials-Page 1
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