SN74AHCT02DG4 [TI]
具有 TTL 兼容型 CMOS 输入的 4 通道、2 输入、4.5V 至 5.5V 或非门 | D | 14 | -40 to 85;
| 型号： | SN74AHCT02DG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 TTL 兼容型 CMOS 输入的 4 通道、2 输入、4.5V 至 5.5V 或非门 | D | 14 | -40 to 85 栅 光电二极管 逻辑集成电路 触发器 栅极 |
| 文件： | 总6页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54AHCT02, SN74AHCT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS262I – DECEMBER 1995 – REVISED JANUARY 2000
SN54AHCT02 . . . J OR W PACKAGE
SN74AHCT02 . . . D, DB, DGV, N, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Process
Inputs Are TTL-Voltage Compatible
Latch-Up Performance Exceeds 250 mA Per
JESD 17
1Y
1A
V
CC
1
2
3
4
5
6
7
14
13
12
11
4Y
4B
4A
1B
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
2Y
2A
10 3Y
9
8
2B
3B
3A
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) DIPs
GND
SN54AHCT02 . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
18
description
4B
NC
4A
1B
NC
2Y
4
5
6
7
8
17
16
These devices contain four independent 2-input
NOR gates that perform the Boolean function
Y = A B or Y = A + B in positive logic.
15 NC
14
9 10 11 12 13
NC
2A
3Y
The SN54AHCT02 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74AHCT02 is characterized for
operation from –40°C to 85°C.
NC – No internal connection
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
B
X
H
L
H
X
L
L
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT02, SN74AHCT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS262I – DECEMBER 1995 – REVISED JANUARY 2000
†
logic symbol
2
≥ 1
1A
1B
2A
2B
3A
3B
4A
4B
1
4
3
1Y
2Y
3Y
4Y
5
6
8
10
13
9
11
12
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
logic diagram (positive logic)
2
8
9
1A
1B
1
4
3A
3B
10
13
1Y
2Y
3Y
4Y
3
5
6
11
12
2A
2B
4A
4B
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT02, SN74AHCT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS262I – DECEMBER 1995 – REVISED JANUARY 2000
recommended operating conditions (see Note 3)
SN54AHCT02 SN74AHCT02
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
5.5
0.8
5.5
V
0
0
0
0
V
I
Output voltage
V
CC
–8
V
CC
–8
V
O
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
mA
mA
ns/V
°C
OH
OL
8
8
20
85
∆t/∆v
20
T
A
–55
125
–40
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
SN54AHCT02 SN74AHCT02
PARAMETER
TEST CONDITIONS
V
UNIT
V
CC
MIN
4.4
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
= –50
A
4.5
OH
OH
OL
OL
V
4.5 V
4.5 V
OH
OL
= –8 mA
= 50
= 8 mA
3.94
3.8
3.8
A
0.1
0.36
±0.1
2
0.1
0.44
±1*
20
0.1
0.44
±1
V
V
I
I
V = V
or GND
or GND,
0 V to 5.5 V
5.5 V
A
A
I
I
CC
CC
V = V
I = 0
O
20
CC
I
One input at 3.4 V,
Other inputs at GND or V
†
5.5 V
1.35
1.5
1.5
10
mA
pF
∆I
CC
CC
C
V = V or GND
I CC
5 V
4
10
i
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V
CC
= 0 V.
†
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or V
CC
.
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
2.4**
3.5**
3.4
SN54AHCT02 SN74AHCT02
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
ns
MIN
MAX
5.5**
5.5**
7.5
MIN
1**
1**
1
MAX
6.5**
6.5**
8.5
MIN
1
MAX
6.5
t
t
PLH
PHL
A or B
A or B
Y
Y
C
C
= 15 pF
= 50 pF
L
L
1
6.5
t
1
8.5
PLH
PHL
ns
t
4.5
7.5
1
8.5
1
8.5
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT02, SN74AHCT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS262I – DECEMBER 1995 – REVISED JANUARY 2000
noise characteristics, V
= 5 V, C = 50 pF, T = 25°C (see Note 4)
CC
L
A
SN74AHCT02
PARAMETER
UNIT
MIN
TYP
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
0.8
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
–0.8
OL
4.7
OH
2
0.8
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
17
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT02, SN74AHCT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS262I – DECEMBER 1995 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
0 V
1.5 V
Timing Input
t
w
t
h
3 V
t
su
3 V
0 V
1.5 V
1.5 V
Input
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
0 V
t
t
t
t
t
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
CC
V
V
+ 0.3 V
OL
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
– 0.3 V
OH
50% V
50% V
CC
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Copyright 2000, Texas Instruments Incorporated
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