SN74AHCT138Q-Q1 [TI]
汽车类 3 线至 8 线解码器/多路解复用器;
| 型号： | SN74AHCT138Q-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 3 线至 8 线解码器/多路解复用器 驱动 复用器 解复用器 解码器 驱动器 |
| 文件： | 总12页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊꢋ ꢌ ꢋꢈ
ꢉ ꢌꢍ ꢎꢁꢏ ꢇ ꢐ ꢊ ꢌꢍ ꢎꢁꢏ ꢑꢏ ꢆꢐꢑ ꢏꢒꢓ ꢑꢏꢔ ꢕꢍꢇꢎ ꢖ ꢍꢏ ꢗꢏ ꢒ
SGDS022A − FEBRUARY 2002 − REVISED APRIL 2008
D OR PW PACKAGE
(TOP VIEW)
D
D
Qualified for Automotive Applications
EPIC (Enhanced-Performance Implanted
CMOS) Process
A
B
V
CC
15 Y0
1
2
3
4
5
6
7
8
16
D
Inputs Are TTL-Voltage Compatible
14
D
Designed Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems
C
Y1
13
12
11
10
9
G2A
G2B
G1
Y2
Y3
Y4
Y5
Y6
D
D
D
Incorporates Three Enable Inputs to
Simplify Cascading and/or Data Reception
Y7
GND
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-833, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
description
The SN74AHCT138Q 3-line to 8-line decoder/demultiplexer is designed to be used in high-performance
memory-decoding and data-routing applications that require very short propagation-delay times. In
high-performance memory systems, this decoder can be used to minimize the effects of system decoding.
When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and
the enable time of the memory usually are less than the typical access time of the memory. This means that
the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
{
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
PACKAGE
T
A
SOIC − D
Tape and reel
Tape and reel
SN74AHCT138QDRQ1
SN74AHCT138QPWRQ1
AHCT138Q
HB138Q
−40°C to 125°C
TSSOP − PW
†
‡
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments.
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Copyright 2008, Texas Instruments Incorporated
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ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉ ꢊꢋꢌꢋ ꢈ
ꢉꢌ ꢍ ꢎ ꢁꢏ ꢇꢐ ꢊ ꢌꢍ ꢎ ꢁ ꢏ ꢑꢏ ꢆꢐ ꢑꢏ ꢒꢓ ꢑ ꢏꢔ ꢕꢍꢇꢎ ꢖ ꢍꢏ ꢗꢏꢒ
SGDS022A − FEBRUARY 2002 − REVISED APRIL 2008
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUTS
G1
G2A
H
X
X
L
G2B
C
X
X
X
L
B
X
X
X
L
A
Y0
H
H
H
L
Y1
H
H
H
H
L
Y2
H
H
H
H
H
L
Y3
H
H
H
H
H
H
L
Y4
H
H
H
H
H
H
H
L
Y5
H
H
H
H
H
H
H
H
L
Y6
H
H
H
H
H
H
H
H
H
L
Y7
H
H
H
H
H
H
H
H
H
H
L
X
X
L
X
H
X
L
L
L
L
L
L
L
L
X
X
X
L
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
L
H
H
H
H
L
H
H
†
logic symbols (alternatives)
BIN/OCT
1
DMUX
15
14
13
12
11
10
9
15
14
13
12
11
10
9
1
2
3
0
1
2
3
4
5
6
7
Y0
0
1
2
3
4
5
6
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
A
B
C
1
2
4
A
B
C
0
2
2
3
0
7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
G
&
&
6
4
6
4
G1
G2A
G2B
G1
G2A
G2B
EN
5
5
7
7
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
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ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊꢋ ꢌ ꢋꢈ
ꢉ ꢌꢍ ꢎꢁꢏ ꢇ ꢐ ꢊ ꢌꢍ ꢎꢁꢏ ꢑꢏꢆ ꢐꢑ ꢏꢒꢓ ꢑꢏꢔ ꢕꢍꢇꢎ ꢖ ꢍꢏ ꢗꢏ ꢒ
SGDS022A − FEBRUARY 2002 − REVISED APRIL 2008
logic diagram (positive logic)
15
Y0
1
A
14
Y1
13
Y2
2
Select
B
Inputs
12
Y3
Data
Outputs
11
10
9
Y4
Y5
3
C
Y6
Y7
4
7
G2A
5
Enable
Inputs
G2B
6
G1
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3
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ꢉꢌ ꢍ ꢎ ꢁꢏ ꢇꢐ ꢊ ꢌꢍ ꢎ ꢁ ꢏ ꢑꢏ ꢆꢐ ꢑꢏ ꢒꢓ ꢑ ꢏꢔ ꢕꢍꢇꢎ ꢖ ꢍꢏ ꢗꢏꢒ
SGDS022A − FEBRUARY 2002 − REVISED APRIL 2008
recommended operating conditions (see Note 3)
MIN
4.5
2
MAX
UNIT
V
V
V
V
V
V
Supply voltage
5.5
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
V
0.8
5.5
V
0
0
V
I
Output voltage
V
CC
−8
V
O
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
mA
mA
ns/V
°C
OH
OL
I
8
∆t/∆v
20
T
A
−40
125
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
4.5
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
V
CC
MIN
4.4
MAX
I
I
I
I
= −50 mA
= −8 mA
= 50 mA
= 8 mA
4.4
3.8
OH
OH
OL
OL
V
4.5 V
4.5 V
OH
OL
3.94
0.1
0.36
0.1
4
0.1
0.5
1
V
V
I
I
V = 5.5 V or GND
0 V to 5.5 V
5.5 V
mA
mA
I
I
V = V
CC
or GND,
I = 0
O
40
CC
I
One input at 3.4 V,
Other inputs at V
†
5.5 V
5 V
1.35
10
1.5
mA
pF
∆I
CC
or GND
CC
or GND
C
V = V
I CC
2
i
†
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or V
CC
.
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
7.6
7.6
6.6
6.6
7
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN
MAX
UNIT
ns
MIN
MAX
10.4
10.4
9.1
t
t
t
t
t
t
t
t
t
t
t
t
1
1
1
1
1
1
1
1
1
1
1
1
12
12
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
A, B, C
G1
Any Y
Any Y
Any Y
Any Y
Any Y
Any Y
C
C
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 50 pF
= 50 pF
= 50 pF
L
L
L
L
L
L
10.5
10.5
11
ns
9.1
9.6
ns
G2A, G2B
A, B, C
G1
7
9.6
11
8.1
8.1
7.1
7.1
7.5
7.5
11.4
11.4
10.1
10.1
10.6
10.6
13
ns
13
11.5
11.5
12
ns
ns
G2A, G2B
12
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊꢋ ꢌ ꢋꢈ
ꢉ ꢌꢍ ꢎꢁꢏ ꢇ ꢐ ꢊ ꢌꢍ ꢎꢁꢏ ꢑꢏꢆ ꢐꢑ ꢏꢒꢓ ꢑꢏꢔ ꢕꢍꢇꢎ ꢖ ꢍꢏ ꢗꢏ ꢒ
SGDS022A − FEBRUARY 2002 − REVISED APRIL 2008
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load,
f = 1 MHz
14
pF
pd
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
PLH PHL
Open
C
C
L
t
/t
V
CC
L
PLZ PZL
(see Note A)
(see Note A)
/t
PHZ PZH
GND
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
1.5 V
Timing Input
0 V
t
w
t
h
3 V
t
su
3 V
0 V
1.5 V
1.5 V
Input
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
t
t
t
t
t
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
CC
V
V
+ 0.3 V
OL
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
− 0.3 V
OH
50% V
CC
50% V
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉ ꢊꢋꢌꢋ ꢈ
ꢉꢌ ꢍ ꢎ ꢁꢏ ꢇꢐ ꢊ ꢌꢍ ꢎ ꢁ ꢏ ꢑꢏ ꢆꢐ ꢑꢏ ꢒꢓ ꢑ ꢏꢔ ꢕꢍꢇꢎ ꢖ ꢍꢏ ꢗꢏꢒ
SGDS022A − FEBRUARY 2002 − REVISED APRIL 2008
APPLICATION INFORMATION
SN74AHCT138Q
BIN/OCT
15
14
13
12
11
10
9
1
2
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
2
3
4
6
4
5
&
V
CC
EN
7
SN74AHCT138Q
BIN/OCT
0
15
14
13
12
11
10
9
1
2
8
A0
A1
A2
1
1
2
3
4
5
6
7
9
2
4
10
11
12
13
14
15
3
6
4
5
&
A3
A4
EN
7
SN74AHCT138Q
BIN/OCT
0
15
14
13
12
11
10
9
1
2
16
17
18
19
20
21
22
23
1
1
2
3
4
5
6
7
2
4
3
6
4
5
&
EN
7
Figure 2. 24-Bit Decoding Scheme
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SGDS022A − FEBRUARY 2002 − REVISED APRIL 2008
APPLICATION INFORMATION
SN74AHCT138Q
BIN/OCT
15
14
13
12
11
10
9
1
2
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
A0
A1
A2
1
2
3
4
6
4
5
&
V
CC
A3
EN
A4
7
SN74AHCT138Q
BIN/OCT
0
15
14
13
12
11
10
9
1
2
8
1
1
2
3
4
5
6
7
9
2
4
10
11
12
13
14
15
3
6
4
5
&
EN
7
SN74AHCT138Q
BIN/OCT
0
15
14
13
12
11
10
9
1
2
16
17
18
19
20
21
22
23
1
1
2
3
4
5
6
7
2
4
3
6
4
5
&
EN
7
SN74AHCT138Q
BIN/OCT
0
15
14
13
12
11
10
9
1
2
24
25
26
27
28
29
30
31
1
1
2
3
4
5
6
7
2
4
3
6
4
5
&
EN
7
Figure 3. 32-Bit Decoding Scheme
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
15-Mar-2010
PACKAGING INFORMATION
Orderable Device
CAHCT138QPWRG4Q1
SN74AHCT138QDRG4Q1
SN74AHCT138QDRQ1
SN74AHCT138QPWRQ1
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
16
16
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
D
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
PW
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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