SN74AHCT174NSR [TI]
HEX D-TYPE FLIP-FLOPS WITH CLEAR;
| 型号： | SN74AHCT174NSR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HEX D-TYPE FLIP-FLOPS WITH CLEAR |
| 文件： | 总6页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54AHCT174, SN74AHCT174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS419F – JUNE 1998 – REVISED APRIL 2002
SN54AHCT174 . . . J OR W PACKAGE
SN74AHCT174 . . . D, DB, DGV, N, NS, OR PW PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
Contain Six Flip-Flops With Single-Rail
Outputs
Applications Include:
– Buffer/Storage Registers
– Shift Registers
CLR
1Q
1D
2D
2Q
3D
3Q
GND
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
6Q
6D
5D
5Q
4D
4Q
CLK
– Pattern Generators
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN54AHCT174 . . . FK PACKAGE
(TOP VIEW)
description
These positive-edge-triggered D-type flip-flops
have a direct clear (CLR) input.
3
2
1 20 19
18 6D
1D
2D
NC
2Q
3D
4
5
6
7
8
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the transition time of the positive-going edge of
CLK. When CLK is at either the high or low level,
the D input has no effect at the output.
17
5D
NC
5Q
4D
16
15
14
9 10 11 12 13
NC – No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
SOIC – D
Tube
SN74AHCT174N
SN74AHCT174N
Tube
SN74AHCT174D
AHCT174
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tube
SN74AHCT174DR
SN74AHCT174NSR
SN74AHCT174DBR
SN74AHCT174PWR
SN74AHCT174DGVR
SNJ54AHCT174J
SNJ54AHCT174W
SNJ54AHCT174FK
–40°C to 85°C
SOP – NS
AHCT174
SSOP – DB
TSSOP – PW
TVSOP – DGV
CDIP – J
HB174
HB174
HB174
SNJ54AHCT174J
SNJ54AHCT174W
SNJ54AHCT174FK
–55°C to 125°C
CFP – W
Tube
LCCC – FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT174, SN74AHCT174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS419F – JUNE 1998 – REVISED APRIL 2002
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
CLR
L
CLK
D
X
H
L
X
↑
L
H
L
H
H
↑
H
L
X
Q
0
logic diagram (positive logic)
1
CLR
9
CLK
3
1D
C1
1D
2
1Q
R
To Five Other Channels
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, and W packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT174, SN74AHCT174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS419F – JUNE 1998 – REVISED APRIL 2002
recommended operating conditions (see Note 3)
SN54AHCT174 SN74AHCT174
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
5.5
0.8
5.5
V
0
0
0
0
V
I
Output voltage
V
CC
V
CC
V
O
I
High-level output current
Low-level output current
Input transition rise or fall time
Operating free-air temperature
–8
–8
mA
mA
ns/V
°C
OH
OL
I
8
8
20
85
∆t ∆v
20
T
–55
125
–40
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
SN54AHCT174 SN74AHCT174
PARAMETER
TEST CONDITIONS
= –50
V
UNIT
CC
MIN
4.4
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
A
4.5
OH
V
4.5 V
4.5 V
V
OH
OL
3.94
3.8
3.8
I
= –8 mA
OH
OL
I
= 50
A
0.1
0.36
±0.1
4
0.1
0.44
±1*
40
0.1
0.44
±1
V
V
I
= 8 mA
OL
I
I
V = 5.5 V or GND
0 V to 5.5 V
5.5 V
A
A
I
I
V = V
or GND,
I = 0
O
40
CC
I
CC
One input at 3.4 V,
Other inputs at V
†
∆I
CC
5.5 V
5 V
1.35
10
1.5
1.5
10
A
or GND
CC
V = V or GND
CC
C
2
pF
i
I
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or V
CC
= 0 V.
CC
†
.
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted)
= 5 V ± 0.5 V
CC
T
= 25°C
SN54AHCT174 SN74AHCT174
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
CLR low
t
Pulse duration
ns
w
CLK high or low
Data
5
5
5
5
5
5
t
t
ns
ns
Setup time before CLK↑
su
CLR inactive
3.5
0
3.5
0
3.5
0
Hold time, data after CLK↑
h
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT174, SN74AHCT174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS419F – JUNE 1998 – REVISED APRIL 2002
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T = 25°C
A
SN54AHCT174 SN74AHCT174
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
TYP
MAX
MIN
80**
65
1**
1**
1**
1
MAX
MIN
80
65
1
MAX
C
C
C
= 15 pF
= 50 pF
= 15 pF
100** 135**
80 115
7.6** 10.4**
L
L
L
f
MHz
ns
max
t
t
t
t
t
t
t
CLR
CLK
CLR
CLK
Any Q
Any Q
Any Q
Any Q
13**
9**
9**
13
13
9
PHL
PLH
PHL
PHL
PLH
PHL
sk(o)
5.8**
5.8**
8.1
7.8**
7.8**
11.4
8.8
1
C
C
C
C
= 15 pF
= 50 pF
= 50 pF
= 50 pF
ns
L
L
L
L
1
9
1
13
10
10
1
ns
6.3
1
10
1
ns
6.3
8.8
1
10
1
1***
ns
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
*** On products compliant to MIL-PRF-38535, this parameter does not apply.
noise characteristics V
= 5 V, C = 50 pF, T = 25°C (see Note 4)
CC
L
A
SN74AHCT174
PARAMETER
UNIT
MIN
TYP
0.8
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
–0.8
OL
4
2
OH
0.8
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
28
pF
pd
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT174, SN74AHCT174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS419F – JUNE 1998 – REVISED APRIL 2002
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
0 V
1.5 V
Timing Input
t
w
t
h
3 V
t
su
3 V
0 V
1.5 V
1.5 V
Input
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
0 V
t
t
t
t
t
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
CC
V
V
+ 0.3 V
OL
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
– 0.3 V
OH
50% V
50% V
CC
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
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Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
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