SN74AHCT1G00_15 [TI]
Single 2-Input Positive-NAND Gate;
| 型号： | SN74AHCT1G00_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Single 2-Input Positive-NAND Gate 栅 |
| 文件： | 总7页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AHCT1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCLS316M – MARCH 1996 – REVISED JANUARY 2003
DBV OR DCK PACKAGE
(TOP VIEW)
Operating Range of 4.5 V to 5.5 V
Max t of 7.1 ns at 5 V
pd
Low Power Consumption, 10-µA Max I
±8-mA Output Drive at 5 V
1
2
3
5
4
CC
A
B
GND
V
Y
CC
Inputs Are TTL-Voltage Compatible
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
The SN74AHCT1G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
‡
Reel of 3000
Reel of 250
Reel of 3000
SN74AHCT1G00DBVR
SN74AHCT1G00DBVT
SN74AHCT1G00DCKR
SOT (SOT-23) – DBV
B00_
–40°C to 85°C
SOT (SC-70) – DCK
BA_
Reel of 250
SN74AHCT1G00DCKT
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
The actual top-side marking has one additional character that designates the assembly/test site.
FUNCTION TABLE
INPUTS
OUTPUT
Y
A
B
H
X
L
H
L
L
H
H
X
logic diagram (positive logic)
1
2
4
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AHCT1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCLS316M – MARCH 1996 – REVISED JANUARY 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
JA
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
V
V
V
V
V
V
Supply voltage
4.5
2
5.5
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
V
0.8
5.5
V
0
0
V
I
Output voltage
V
V
O
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–8
mA
mA
ns/V
°C
OH
OL
8
20
85
∆t/∆v
T
–40
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
V
CC
MIN
4.4
MAX
I
I
I
I
= –50
A
4.5
4.4
3.8
OH
OH
OL
OL
V
V
4.5 V
4.5 V
OH
= –8 mA
= 50
= 8 mA
3.94
A
0.1
0.36
±0.1
1
0.1
0.44
±1
V
OL
I
I
V = 5.5 V or GND
0 V to 5.5 V
5.5 V
A
A
I
I
V = V
or GND,
I = 0
O
10
CC
I
CC
One input at 3.4 V,
V = V or GND
‡
∆I
CC
Other inputs at V
or GND
5.5 V
1.35
10
1.5
10
mA
pF
CC
C
5 V
2
i
I
CC
‡
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or V
.
CC
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AHCT1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCLS316M – MARCH 1996 – REVISED JANUARY 2003
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
5
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN
MAX
UNIT
ns
MIN
MAX
6.2
t
t
t
t
1
1
1
1
7.1
7.1
9
PLH
PHL
PLH
PHL
A or B
A or B
Y
Y
C
C
= 15 pF
= 50 pF
L
L
5
6.2
5.5
5.5
7.9
ns
7.9
9
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
10.5
pF
pd
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AHCT1G00
SINGLE 2-INPUT POSITIVE-NAND GATE
SCLS316M – MARCH 1996 – REVISED JANUARY 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
1.5 V
Timing Input
0 V
t
w
t
h
3 V
t
su
3 V
0 V
1.5 V
1.5 V
Input
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
t
t
t
t
t
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
CC
V
V
+ 0.3 V
OL
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
– 0.3 V
OH
50% V
50% V
CC
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002
DCK (R-PDSO-G5)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,10
0,65
5
4
0,13 NOM
1,40 2,40
1,10 1,80
1
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
0,10
1,10
0,80
0,10
0,00
4093553-2/D 01/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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