SN74AHCT1G86-Q1 [TI]
具有 TTL 兼容型 CMOS 输入的汽车类单路 2 输入、4.5V 至 5.5V XOR（异或）门;
| 型号： | SN74AHCT1G86-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 TTL 兼容型 CMOS 输入的汽车类单路 2 输入、4.5V 至 5.5V XOR（异或）门 石英晶振 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AHCT1G86Q-Q1
www.ti.com
SCLS721 –DECEMBER 2010
SINGLE 2-INPUT EXCLUSIVE-OR GATE
Check for Samples: SN74AHCT1G86Q-Q1
1
FEATURES
DCK PACKAGE
(TOP VIEW)
•
•
•
•
•
•
Qualified For Automotive Applications
Operating Range of 4.5 V to 5.5 V
Max tpd of 8 ns at 5 V
1
2
3
5
4
A
B
V
Y
CC
Low Power Consumption, 10-mA Max ICC
±8-mA Output Drive at 5 V
GND
Inputs Are TTL-Voltage Compatible
DESCRIPTION
The SN74AHCT1G86 is a single 2-input exclusive-OR gate. The device performs the Boolean function Y = A ⊕
B or Y = AB + AB in positive logic.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
B5S
–40°C to 125°C
SOT (SC70) – DCK Reel of 3000
CAHCT1G86QDCKRQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTION TABLE
INPUTS
OUTPUT
Y
A
L
B
L
L
H
H
L
L
H
L
H
H
H
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
SN74AHCT1G86Q-Q1
SCLS721 –DECEMBER 2010
www.ti.com
EXCLUSIVE-OR LOGIC
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
EXCLUSIVE OR
= 1
These five equivalent exclusive-OR symbols are valid for an SN74AHCT1G86 gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT
=
EVEN-PARITY ELEMENT
2k
ODD-PARITY ELEMENT
2k + 1
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
Theoutput is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
ABSOLUTE MAXIMUM RATINGS(1)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Output voltage range applied in the high- or low-state(2)
7
7
V
VO
IIK
VCC + 0.5
–20
V
Input clamp current
VI < 0 V
V
IOK
IO
Output clamp current
VO < 0 V or VO > VCC
VO = 0 V to VCC
±20
mA
mA
mA
°C/W
°C
Continuous output current
Continuous current through VCC or GND
Thermal impedance(3)
±25
±50
qJA
DCK package
252
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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Product Folder Link(s): SN74AHCT1G86Q-Q1
SN74AHCT1G86Q-Q1
www.ti.com
SCLS721 –DECEMBER 2010
RECOMMENDED OPERATING CONDITIONS(1)
MIN
4.5
2
MAX
UNIT
V
VCC
VIH
VIL
Supply voltage
5.5
High-level input voltage
Low-level input voltage
Input voltage
V
0.8
5.5
VCC
–8
V
VI
0
0
V
VO
Output voltage
V
IOH
IOL
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
mA
mA
ns/V
°C
8
Δt/ΔV
TA
20
–40
125
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
Copyright © 2010, Texas Instruments Incorporated
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3
Product Folder Link(s): SN74AHCT1G86Q-Q1
SN74AHCT1G86Q-Q1
SCLS721 –DECEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
TA = 25°C
TYP
PARAMETER
TEST CONDITIONS
VCC
MIN MAX UNIT
MIN
4.4
MAX
IOH = –50 mA
IOH = –8 mA
IOL = 50 mA
IOL = 8 mA
4.5
4.4
VOH
4.5 V
4.5 V
V
3.94
3.8
0.1
0.36
±0.1
1
0.1
V
VOL
0.44
II
VI = 5.5 V or GND
VI = VCC or GND,
One input at 3.4 V,
VI = VCC or GND
0 V to 5.5 V
5.5 V
±1
10
mA
mA
mA
pF
ICC
IO = 0 A
(1)
ΔICC
Other inputs at GND or VCC
5.5 V
1.35
10
1.5
10
CI
5 V
(1) This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC
.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 5 V ±0.5 V, TA = –40°C to 125°C, see Figure 1
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN
MAX UNIT
MIN
TYP
5.5
MAX
7.9
tPLH
tPHL
1
1
9
A or B
Y
CL = 50 pF
ns
9
5.5
7.9
OPERATING CHARACTERISTICS
VCC = 5 V ±0.5 V, TA = –40°C to 125°C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
No load, f = 1 MHz
18
pF
4
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AHCT1G86Q-Q1
SN74AHCT1G86Q-Q1
www.ti.com
SCLS721 –DECEMBER 2010
PARAMETER MEASUREMENT INFORMATION
V
CC
S1
Open
GND
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
PLH PHL
/t
PLZ PZL
/t
PHZ PZH
Open
C
(see Note A)
C
L
(see Note A)
t
V
CC
GND
L
Open Drain
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
1.5 V
Timing Input
0 V
t
w
t
h
3 V
t
su
3 V
0 V
1.5 V
1.5 V
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
PLZ
t
t
t
PZL
PLH
PHL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
50% V
CC
50% V
CC
CC
CC
V
S1 at V
CC
(see Note B)
V
V
+ 0.3 V
OL
V
OL
OL
t
t
PZH
t
PHL
PLH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
– 0.3 V
OH
50% V
50% V
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output
control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf
≤3 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 2010, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CAHCT1G86QDCKRQ1
ACTIVE
SC70
DCK
5
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
B5S
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AHCT1G86-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Catalog: SN74AHCT1G86
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CAHCT1G86QDCKRQ1
SC70
DCK
5
3000
180.0
8.4
2.47
2.3
1.25
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SC70 DCK
SPQ
Length (mm) Width (mm) Height (mm)
202.0 201.0 28.0
CAHCT1G86QDCKRQ1
5
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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