SN74AHCT244-Q1 [TI]
OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS; 八路缓冲器/驱动器，具有三态输出
| 型号： | SN74AHCT244-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS |
| 文件： | 总13页 (文件大小：596K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇꢈ ꢃꢃ ꢉꢊ ꢋ
ꢌ ꢆꢇꢄꢍ ꢎꢏꢐ ꢐ ꢑ ꢒꢓ ꢔꢒ ꢕ ꢖꢑ ꢒ
ꢗ ꢕꢇ ꢅ ꢘ ꢉꢀꢇꢄꢇ ꢑ ꢌ ꢏꢇ ꢙꢏ ꢇꢀ
SCLS529C − AUGUST 2003 − REVISED APRIL 2008
DW OR PW PACKAGE
(TOP VIEW)
D
D
Qualified for Automotive Applications
ESD Protection Exceeds 1000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
D
D
EPIC (Enhanced-Performance Implanted
CMOS) Process
Inputs Are TTL-Voltage Compatible
description/ordering information
This octal buffer/driver is designed specifically to
improve both the performance and density of 3-state
memory-address drivers, clock drivers, and
bus-oriented receivers and transmitters.
The SN74AHCT244 is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs.
When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are
in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE shall be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
{
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
PACKAGE
T
A
−40°C to 85°C
−40°C to 125°C
TSSOP − PW Tape and reel SN74AHCT244IPWRQ1
SOIC − DW Tape and reel SN74AHCT244QDWRQ1
TSSOP − PW Tape and reel SN74AHCT244QPWRQ1
AHCT244I
AHCT244Q
AHCT244Q
†
For the most current package and ordering information, see the Package Option Addendum at the end of
this document, or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
‡
FUNCTION TABLE
(each 4-bit buffer/driver)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
H
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments.
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Copyright 2008, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢌꢆ ꢇꢄ ꢍ ꢎ ꢏ ꢐꢐ ꢑꢒ ꢓꢔ ꢒꢕ ꢖ ꢑꢒ
ꢗꢕ ꢇꢅ ꢘ ꢉꢀꢇꢄꢇ ꢑ ꢌꢏꢇ ꢙ ꢏꢇꢀ
SCLS529C − AUGUST 2003 − REVISED APRIL 2008
logic diagram (positive logic)
1
19
11
1OE
2OE
2A1
2
18
16
14
12
9
7
5
3
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
1A1
4
13
15
17
1A2
2A2
2A3
2A4
6
1A3
8
1A4
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mA
Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
JA
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
V
V
V
V
V
V
Supply voltage
4.5
2
5.5
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
V
0.8
5.5
V
0
0
V
I
Output voltage
V
V
O
CC
−8
I
I
High-level output current
Low-level output current
mA
mA
OH
8
OL
I-suffix device
Q-suffix device
−40
−40
85
T
A
Operating free-air temperature
°C
125
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇꢈ ꢃꢃ ꢉꢊ ꢋ
ꢌ ꢆꢇꢄꢍ ꢎꢏꢐ ꢐ ꢑꢒ ꢓꢔ ꢒ ꢕꢖ ꢑ ꢒ
ꢗ ꢕꢇ ꢅ ꢘ ꢉꢀꢇꢄꢇ ꢑ ꢌ ꢏꢇ ꢙꢏ ꢇꢀ
SCLS529C − AUGUST 2003 − REVISED APRIL 2008
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
4.5
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
V
CC
MIN
4.4
MAX
I
I
I
I
= −50 mA
= −8 mA
= 50 mA
= 8 mA
4.4
3.8
OH
OH
OL
OL
V
OH
4.5 V
4.5 V
3.94
0.1
0.36
0.25
0.1
0.1
0.44
2.5
1
V
OL
V
I
I
I
V
= V
O CC
or GND
5.5 V
0 V to 5.5 V
5.5 V
mA
mA
mA
OZ
V = 5.5 V or GND
I
I
V = V
CC
or GND,
I = 0
O
4
40
CC
I
One input at 3.4 V,
Other inputs at V
†
5.5 V
1.35
10
1.5
mA
∆I
CC
or GND
CC
or GND
C
C
V = V
I CC
5 V
5 V
2.5
3
pF
pF
i
V
O
= V or GND
CC
o
†
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or V
CC
.
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
5.4
5.4
7.7
7.7
5
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN
MAX
UNIT
ns
MIN
MAX
7.4
t
1
1
1
1
1
1
1
1
1
1
1
1
8.5
8.5
12
12
10
10
9.5
9.5
13
13
13
13
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
C
C
C
= 15 pF
= 15 pF
= 15 pF
L
L
L
t
t
t
t
t
t
t
t
t
t
t
t
7.4
10.4
10.4
9.4
ns
OE
OE
ns
5
9.4
5.9
5.9
8.2
8.2
8.8
8.8
8.4
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
A
Y
Y
Y
C
C
= 50 pF
= 50 pF
ns
ns
L
L
8.4
11.4
11.4
11.4
11.4
1
OE
OE
C
C
= 50 pF
= 50 pF
ns
ns
L
L
noise characteristics, V
= 5 V, C = 50 pF, T = 25°C (see Note 4)
CC
L
A
PARAMETER
MIN
TYP
MAX
UNIT
V
V
V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
4.1
V
V
V
OH(V)
IH(D)
IL(D)
OH
2
0.8
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
8.2
pF
pd
3
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ꢗꢕ ꢇꢅ ꢘ ꢉꢀꢇꢄꢇ ꢑ ꢌꢏꢇ ꢙ ꢏꢇꢀ
SCLS529C − AUGUST 2003 − REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
0 V
1.5 V
Timing Input
t
w
t
h
3 V
t
su
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
0 V
t
t
t
t
t
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
CC
V
V
+ 0.3 V
OL
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
− 0.3 V
OH
50% V
CC
50% V
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
CAHCT244IPWRG4Q1
CAHCT244QDWRG4Q1
CAHCT244QPWRG4Q1
SN74AHCT244IPWRQ1
SN74AHCT244QDWRQ1
SN74AHCT244QPWRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
SOIC
PW
DW
PW
PW
DW
PW
20
20
20
20
20
20
2000
2000
2000
2000
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
TSSOP
TSSOP
SOIC
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TSSOP
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2011
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AHCT244-Q1 :
Catalog: SN74AHCT244
•
Enhanced Product: SN74AHCT244-EP
•
Military: SN54AHCT244
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CAHCT244QPWRG4Q1 TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
CAHCT244QPWRG4Q1
2000
Pack Materials-Page 2
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