SN74AHCT245QPWRQ1 [TI]
具有三态输出的八路总线收发器 | PW | 20 | -40 to 125;
| 型号： | SN74AHCT245QPWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有三态输出的八路总线收发器 | PW | 20 | -40 to 125 总线收发器 |
| 文件： | 总18页 (文件大小：1046K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AHCT245-Q1
ZHCSRY4 –APRIL 2023
SN74AHCT245-Q1 具有三态输出的汽车类八路总线收发器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
– 器件温度等级1：–40°C 至+125°C，TA
• 输入兼容TTL 电压
SN74AHCT245-Q1 八路总线收发器专为数据总线之间
的异步双向通信而设计。这些器件的工作电压范围为
4.5V 至5.5V。
• 闩锁性能超过250mA，
封装信息(1)
符合JESD 17 规范
封装尺寸（NOM）
器件型号
封装
• ESD 保护性能超过JESD 22 规范要求
– 2000V 人体放电模型(A114-A)
– 200V 机器放电模型(A115-A)
– 1000V 充电器件模型(C101)
SN74AHCT245-Q1 PW（TSSOP，20） 6.50mm × 4.40mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 启用或禁用数字信号
• 在控制器复位期间保持信号
• 对开关进行去抖
简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCLS910
SN74AHCT245-Q1
ZHCSRY4 –APRIL 2023
www.ti.com.cn
Table of Contents
8.2 Functional Block Diagram...........................................9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes............................................9
9 Application and Implementation..................................10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................11
11 Layout........................................................................... 11
11.1 Layout Guidelines....................................................11
11.2 Layout Example.......................................................11
12 Device and Documentation Support..........................12
12.1 接收文档更新通知................................................... 12
12.2 支持资源..................................................................12
12.3 Trademarks.............................................................12
12.4 静电放电警告.......................................................... 12
12.5 术语表..................................................................... 12
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................6
6.7 Noise Characteristics..................................................6
6.8 Operating Characteristics........................................... 6
6.9 Typical Characteristics................................................7
7 Parameter Measurement Information............................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
Information.................................................................... 12
4 Revision History
DATE
REVISION
NOTES
August 2022
*
Initial Release
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5 Pin Configuration and Functions
DIR
VCC
OE
20
19
18
17
16
15
1
2
3
A1
A2
B1
B2
B3
B4
4
5
A3
A4
A5
A6
6
7
B5
B6
B7
14
13
12
11
A7
8
A8
9
GND
B8
10
图5-1. SN74AHCT245-Q1: PW Package, 20-Pin TSSOP (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
DIR
A1
NO.
1
Direction Pin
—
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A1 Input/Output
A2 Input/Output
A3 Input/Output
A4 Input/Output
A5 Input/Output
A6 Input/Output
A7 Input/Output
A8 Input/Output
Ground Pin
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
GND
B8
10
11
12
13
14
15
16
17
18
19
20
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
B8 Input/Output
B7 Input/Output
B6 Input/Output
B5 Input/Output
B4 Input/Output
B3 Input/Output
B2 Input/Output
B1 Input/Output
Output Enable
Power Pin
B7
B6
B5
B4
B3
B2
B1
OE
VCC
—
(1) I = input, O = output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
V
VCC
VI
Supply voltage range
7
7
Input voltage range(2)
Control inputs
Control inputs
V
VO
IIK
Output voltage range(2)
Input clamp current
VCC + 0.5
V
VI < 0
mA
mA
mA
mA
–20
±20
±25
±75
IOK
IO
Output clamp current
VO < 0 or VO > VCC
VO = 0 to VCC
Continuous output current
Continuous current through VCC or GND
(1) Operation outside the Absolute Maximum Rating may cause permanent device damage. Absolute Maximum Rating do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Condition. If
used outside the Recommended Operating Condition but within the Absolute Maximum Rating, the device may not be fully functional,
and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
150
°C
–65
Human body model (HBM), per AEC Q100-002 HBM ESD
Classification Level 2(1)
±2000
±1000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per AEC Q100-011 CDM ESD
Classification Level C4B
(1) AEC Q100-002 indicate that HBM stressing shall be in accordrance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
SN74AHCT245-Q1
UNIT
MIN
4.5
2
MAX
VCC
VIH
VIL
Supply voltage
5.5
V
V
High-level input voltage
Low-level Input voltage
Input voltage
0.8
5.5
VCC
–8
8
V
VI
0
0
V
VO
Output voltage
V
IOH
IOL
High-level output current
Low-level output current
Input Transition rise and fall rate
Operating free-air temperature
mA
mA
ns/V
°C
20
Δt/Δv
TA
125
–40
(1) All unused inputs of the device must be held at VCC or GND for proper device operation. Refer to the TI application report, Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.
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English Data Sheet: SCLS910
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6.4 Thermal Information
SN74AHCT245-Q1
THERMAL METRIC(1)
PW
20 PINS
102.8
36.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
53.8
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.5
ψJT
53.3
ψJB
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
–40°C to 125°C
PARAMETER
TEST CONDITIONS
VCC
4.5 V
4.5 V
UNIT
MIN
4.4
TYP
MAX
MIN
4.4
MAX
4.5
IOH = –50 µA
VOH
V
3.94
3.7
IOH = –8 mA
IOL = 50 µA
IOH = 8 mA
0.1
0.1
VOL
V
0.36
0.44
0 to
5.5 V
II
OE or DIR
VI = 5.5 V or GND
±0.1
±1
µA
IOZ
ICC
A or B inputs(1)
VO = VCC or GND
VI = VCC or GND,
One input at 3.4 V,
5.5 V
5.5 V
±.25
4
±2.5
40
µA
µA
IO = 0
(2)
5.5 V
1.35
10
1.5
mA
ΔICC
Other inputs at VCC or GND
Ci
OE or DIR
VI = VCC or GND
5 V
5 V
2.5
4
pF
pF
Cio
A or B inputs
VI = VCC or GND
(1) For I/O ports, the parameter IOZ includes the input leakage current.
(2) This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC
.
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6.6 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted)
TA = 25°C
–40°C to 125°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
ns
TYP
4.5
4.5
8.9
8.9
9.2
9.2
5.3
5.3
9.7
9.7
10
MAX
7.7
MIN
1
MAX
10
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsk(o)
A or B
OE
B or A
A or B
A or B
B or A
A or B
A or B
CL = 15 pF
CL = 15 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
7.7
1
10
13.8
13.8
14.4
14.4
8.7
1
16
ns
1
16
1
16.5
16.5
11
OE
ns
1
1
A or B
OE
ns
8.7
1
11
14.8
14.8
15.4
15.4
1
1
17
ns
1
17
1
17.5
17.5
OE
CL = 50 pF
CL = 50 pF
ns
ns
10
1
6.7 Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C(1)
SN74AHCT245-Q1
PARAMETER
UNIT
MIN
TYP MAX
VOH(V)
VIH(D)
VIL(D)
Quiet output, minimum dynamic VOH
4
V
V
V
High-level dynamic input voltage
Low-level dynamic input voltage
2
0.8
(1) Characteristics are for surface-mount packages only.
6.8 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
pF
Cpd
Power dissipation capacitance
13
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English Data Sheet: SCLS910
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6.9 Typical Characteristics
图6-1. SN74AHCT245 TPD vs Temperature, 15 pF Load
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7 Parameter Measurement Information
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤1 MHz, ZO = 50 Ω, tr ≤3 ns,
tf ≤3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
图7-1. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SNx7ACHT245 octal bus transceivers are designed for asynchronous two-way communication between
data buses. The control-function implementation minimizes external timing requirements. The SN74AHCT245-
Q1 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on
the logic level at the direction–control (DIR) input. The output-enable (OE) input can be used to disable the
device so that the buses effectively are isolated. For the high-impedance state during power up or power down,
OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the
current-sinking capability of the driver.
8.2 Functional Block Diagram
图8-1. Logic Diagram (Positive Logic)
8.3 Feature Description
• VCC is optimized at 5 V
• Allows up voltage translation from 3.3 V to 5 V
– Inputs accept VIH levels of 2 V
• Slow edge rates minimize output ringing
8.4 Device Functional Modes
表8-1. Function Table
(Each Transceiver)
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The SN74AHCT245 is a low drive CMOS device that can be used for a multitude of bus interface type
applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs. The input switching levels have been lowered to accommodate TTL inputs of 0.8 V
VIL and 2 V VIH. This feature makes it ideal for translating up from 3.3 V to 5 V. The following figure shows this
type of translation.
9.2 Typical Application
图9-1. Typical Application Diagram
9.2.1 Design Requirements
This device uses CMOS technology and has a balanced output drive. Take care to avoid bus contention,
because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into
light loads so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
• Recommended input conditions:
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
.
• Recommend output conditions:
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC
.
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English Data Sheet: SCLS910
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9.2.3 Application Curves
5
0 ꢀ
22 ꢀ
50 ꢀ
4
3.3
2
1
0
-1
-2
0
15
30
45
Time (ns)
60
75
90 100
图9-2. Typical Application Curve
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for
each power pin. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. A
0.1 μf and a 1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the
power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple-bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. 图 11-1 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the
part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled.
11.2 Layout Example
V
cc
Input
Unused Input
Output
Output
Unused Input
Input
图11-1. Layout Diagram
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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3-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74AHCT245QPWRQ1
ACTIVE
TSSOP
PW
20
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT245Q
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AHCT245-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-May-2023
Catalog : SN74AHCT245
•
Military : SN54AHCT245
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
•
Military - QML certified for Military and Defense Applications
Addendum-Page 2
PACKAGE OUTLINE
PW0020A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
5.85
6.6
6.4
NOTE 3
10
B
11
0.30
20X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.5)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
11
10
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
20X (1.5)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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