SN74AHCT367PWR [TI]
HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS; HEX缓冲器和线路驱动器，具有三态输出
| 型号： | SN74AHCT367PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总6页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54AHCT367, SN74AHCT367
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS418F – JUNE 1998 – REVISED MAY 2002
SN54AHCT367 . . . J OR W PACKAGE
SN74AHCT367 . . . D, DB, DGV, N, NS, OR PW PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
True Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
1OE
1A1
1Y1
1A2
1Y2
1A3
1Y3
GND
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
2OE
2A2
2Y2
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
12 2A1
– 1000-V Charged-Device Model (C101)
11
10
9
2Y1
1A4
1Y4
description
The ’AHCT367 devices are designed specifically
to improve both the performance and density of
3-state memory address drivers, clock drivers,
and bus-oriented receivers and transmitters.
These devices are organized as dual 4-line
and 2-line buffers/drivers with active-low
output-enable (1OE and 2OE) inputs. When OE is
low, the device passes noninverted data from the
A inputs to the Y outputs. When OE is high, the
outputs are in the high-impedance state.
SN54AHCT367 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
2A2
2Y2
NC
1Y1
1A2
NC
4
5
6
7
8
17
16
15 2A1
14
9 10 11 12 13
1Y2
1A3
To ensure the high-impedance state during power
2Y1
up or power down, OE should be tied to V
CC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
NC – No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
SOIC – D
Tube
SN74AHCT367N
SN74AHCT367N
Tube
SN74AHCT367D
AHCT367
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tube
SN74AHCT367DR
SN74AHCT367NSR
SN74AHCT367DBR
SN74AHCT367PWR
–40°C to 85°C
SOP – NS
AHCT367
HB367
SSOP – DB
TSSOP – PW
TVSOP – DGV
CDIP – J
HB367
SN74AHCT367DGVR HB367
SNJ54AHCT367J
SNJ54AHCT367W
SNJ54AHCT367FK
SNJ54AHCT367J
–55°C to 125°C
CFP – W
Tube
SNJ54AHCT367W
SNJ54AHCT367FK
LCCC – FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT367, SN74AHCT367
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS418F – JUNE 1998 – REVISED MAY 2002
FUNCTION TABLE
(each buffer/driver)
INPUTS
OUTPUT
Y
OE
A
X
H
L
H
L
L
Z
H
L
logic diagram (positive logic)
1
15
1OE
2OE
2A1
2
3
12
11
1A1
1Y1
2Y1
To Three Other Channels
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, and W packages.
To One Other Channel
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT367, SN74AHCT367
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS418F – JUNE 1998 – REVISED MAY 2002
recommended operating conditions (see Note 3)
SN54AHCT367 SN74AHCT367
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
5.5
0.8
5.5
V
0
0
0
0
V
I
Output voltage
V
CC
V
CC
V
O
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–8
–8
mA
mA
ns/V
°C
OH
OL
I
8
8
20
85
∆t/∆v
20
T
–55
125
–40
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
SN54AHCT367 SN74AHCT367
PARAMETER
TEST CONDITIONS
= –50
V
UNIT
V
CC
MIN
4.4
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
A
4.5
OH
OH
OL
OL
V
4.5 V
4.5 V
OH
OL
= –8 mA
= 50
= 8 mA
3.94
3.8
3.8
A
0.1
0.36
0.1
0.44
±1*
0.1
0.44
±1
V
V
I
I
I
V = 5.5 V or GND
0 V to 5.5 V
5.5 V
±0.1*
A
A
I
I
V = V
or GND,
I
O
CC
= V
±0.25
4
±2.5
40
±2.5
40
OZ
CC
V
or GND, OE = V
CC
or GND,
IH
= 0
V = V
I
O
5.5 V
A
I
CC
One input at 3.4 V,
Other inputs at V
†
5.5 V
1.35
10
1.5
10
1.5
10
mA
∆I
CC
or GND
CC
or GND
C
C
V = V
5 V
5 V
2.5
5
pF
pF
i
I
CC
= V
V
or GND
o
O
CC
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or V
CC
= 0 V.
CC
†
.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT367, SN74AHCT367
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS418F – JUNE 1998 – REVISED MAY 2002
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
2.5*
2.5*
3.5*
2.8*
3.1*
2.8*
3.5
SN54AHCT367 SN74AHCT367
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
ns
MIN
MAX
4.8*
4.8*
8*
MIN
1*
1*
1*
1*
1*
1*
1
MAX
6.5*
6.5*
9.5*
8.5*
9.5*
8.5*
7.5
MIN
1
MAX
5.5
5.5
8.5
7.5
8.5
7.5
6.5
6.5
9.5
8.5
9.5
8.5
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
Y
Y
Y
C
C
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 50 pF
= 50 pF
= 50 pF
L
L
L
L
L
L
1
1
ns
OE
OE
A
7*
1
8*
1
ns
7*
1
5.8
5.8
9
1
ns
3.3
1
7.5
1
4.5
1
10.5
9.5
1
ns
OE
OE
3.7
8
1
1
4.1
9
1
10.5
9.5
1
ns
3.6
8
1
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
= 5 V, C = 50 pF, T = 25°C (see Note 4)
CC
L
A
SN74AHCT367
PARAMETER
UNIT
MIN
TYP
0.4
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
–0.4
4.7
OL
OH
2
0.8
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
22
pF
pd
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT367, SN74AHCT367
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS418F – JUNE 1998 – REVISED MAY 2002
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
0 V
1.5 V
Timing Input
t
w
t
h
3 V
t
su
3 V
0 V
1.5 V
1.5 V
Input
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
0 V
t
t
t
t
t
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
CC
V
V
+ 0.3 V
OL
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
– 0.3 V
OH
50% V
50% V
CC
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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in which TI products or services are used. Information published by TI regarding third–party products or services
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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
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Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
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