SN74AHCT595DBLE [TI]
AHCT/VHCT SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, PLASTIC, SSOP-16;
| 型号： | SN74AHCT595DBLE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AHCT/VHCT SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, PLASTIC, SSOP-16 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总20页 (文件大小：1030K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCLS374L − MAY 1997 − REVISED FEBRUARY 2004
SN54AHCT595 . . . J OR W PACKAGE
SN74AHCT595 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
Inputs Are TTL-Voltage Compatible
8-Bit Serial-In, Parallel-Out Shift
Shift Register Has Direct Clear
Q
Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
B
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Q
C
D
A
Q
SER
OE
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Q
E
Q
12 RCLK
F
11
10
9
Q
SRCLK
SRCLR
G
− 1000-V Charged-Device Model (C101)
Q
H
GND
Q
H′
description/ordering information
The ’AHCT595 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel
3-state outputs. Separate clocks are provided for
the shift and storage registers. The shift register
has a direct overriding clear (SRCLR) input, serial
(SER) input, and serial outputs for cascading.
When the output-enable (OE) input is high, the
outputs are in the high-impedance state.
SN54AHCT595 . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
18
SER
OE
Q
4
5
6
7
8
D
Q
17
16
E
NC
NC
15 RCLK
14
9 10 11 12 13
Q
F
Both the shift register clock (SRCLK) and storage
register clock (RCLK) are positive-edge triggered.
If both clocks are connected together, the shift
register always is one clock pulse ahead of the
storage register.
SRCLK
Q
G
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube
SN74AHCT595N
SN74AHCT595N
Tube
SN74AHCT595D
AHCT595
Tape and reel
Tape and reel
Tape and reel
Tube
SN74AHCT595DR
SN74AHCT595NSR
SN74AHCT595DBR
SN74AHCT595PW
SN74AHCT595PWR
SNJ54AHCT595J
SNJ54AHCT595W
SNJ54AHCT595FK
SOP − NS
AHCT595
HB595
−40°C to 85°C
SSOP − DB
TSSOP − PW
HB595
Tape and reel
Tube
CDIP − J
CFP − W
LCCC − FK
SNJ54AHCT595J
SNJ54AHCT595W
SNJ54AHCT595FK
Tube
−55°C to 125°C
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
ꢖ ꢁ ꢘꢑꢀꢀ ꢕ ꢇꢅ ꢑꢐꢓ ꢎꢀ ꢑ ꢁ ꢕꢇꢑꢙ ꢚꢛ ꢜꢝ ꢞꢟꢠ ꢡꢢꢣ ꢤꢚ ꢠꢟ ꢤꢚꢥ ꢜꢤꢝ ꢗꢐ ꢕ ꢙ ꢖ ꢆꢇ ꢎꢕ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢂꢈ ꢂꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇꢂ ꢈ ꢂ
ꢋꢌ ꢍꢎ ꢇ ꢀꢅ ꢎ ꢏ ꢇ ꢐ ꢑꢒ ꢎꢀ ꢇꢑ ꢐꢀ
ꢓꢎ ꢇ ꢅ ꢔ ꢌꢀꢇꢄꢇ ꢑ ꢕꢖꢇ ꢗ ꢖꢇ ꢐꢑ ꢒ ꢎꢀ ꢇꢑ ꢐꢀ
SCLS374L − MAY 1997 − REVISED FEBRUARY 2004
FUNCTION TABLE
INPUTS
FUNCTION
Outputs Q −Q are disabled.
SER SRCLK SRCLR RCLK
OE
H
X
X
X
X
X
X
X
X
L
X
X
X
A
H
L
Outputs Q −Q are enabled.
A H
X
Shift register is cleared.
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
L
↑
H
X
X
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
H
X
↑
H
X
X
X
X
X
↑
Shift-register data is stored in the storage register.
2
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SCLS374L − MAY 1997 − REVISED FEBRUARY 2004
logic diagram (positive logic)
13
OE
12
RCLK
10
SRCLR
11
SRCLK
14
SER
Q
Q
1D
C1
R
3D
C3
15
1
Q
Q
Q
Q
A
B
2D
C2
3D
C3
R
2D
C2
R
3D
C3
Q
Q
2
3
Q
Q
Q
Q
C
D
2D
C2
3D
C3
R
2D
C2
R
3D
C3
Q
Q
Q
4
5
6
Q
Q
Q
Q
Q
Q
E
F
2D
C2
R
3D
C3
2D
C2
3D
C3
G
R
2D
C2
R
3D
C3
Q
7
9
Q
Q
Q
H
H′
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
3
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SCLS374L − MAY 1997 − REVISED FEBRUARY 2004
timing diagram
SRCLK
SER
RCLK
SRCLR
OE
Q
Q
A
B
Q
Q
C
D
Q
E
Q
F
Q
G
Q
H
Q
H’
NOTE:
implies that the output is in 3-State mode.
4
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SCLS374L − MAY 1997 − REVISED FEBRUARY 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54AHCT595 SN74AHCT595
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
5.5
0.8
5.5
V
0
0
0
0
V
I
Output voltage
V
V
V
O
CC
−8
CC
−8
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
mA
mA
ns/V
°C
OH
8
8
20
85
OL
∆t/∆v
20
T
A
−55
125
−40
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
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5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢂꢈ ꢂꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇꢂ ꢈ ꢂ
ꢋꢌ ꢍꢎ ꢇ ꢀꢅ ꢎ ꢏ ꢇ ꢐ ꢑꢒ ꢎꢀ ꢇꢑ ꢐꢀ
ꢓꢎ ꢇ ꢅ ꢔ ꢌꢀꢇꢄꢇ ꢑ ꢕꢖꢇ ꢗ ꢖꢇ ꢐꢑ ꢒ ꢎꢀ ꢇꢑ ꢐꢀ
SCLS374L − MAY 1997 − REVISED FEBRUARY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
4.5
SN54AHCT595 SN74AHCT595
PARAMETER
TEST CONDITIONS
V
UNIT
V
CC
MIN
4.4
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
= −50 mA
= −8 mA
= 50 mA
= 8 mA
OH
OH
OL
OL
V
4.5 V
4.5 V
OH
OL
3.94
3.8
3.8
0.1
0.36
0.1
0.1
0.44
1*
0.1
0.44
1
V
V
I
I
I
V = 5.5 V or GND
0 V to 5.5 V
5.5 V
mA
mA
mA
I
I
V
= V
CC
or GND, Q −Q
H
0.25
4
2.5
40
2.5
40
OZ
CC
O
A
V = V
CC
or GND,
I
O
= 0
5.5 V
I
One input at 3.4V,
Other inputs at V
†
5.5 V
2
2.2
2.2
10
mA
∆I
CC
or GND
CC
or GND
C
C
V = V
I CC
5 V
5 V
3
10
pF
pF
i
V = V
O CC
or GND
5.5
o
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V
= 0 V.
CC
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or V
†
.
CC
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
SN54AHCT595 SN74AHCT595
A
UNIT
MIN
5
MAX
MIN
5.5
5.5
5
MAX
MIN
5.5
5.5
5
MAX
SRCLK high or low
RCLK high or low
SRCLR low
5
t
w
Pulse duration
ns
5
SER before SRCLK↑
SRCLK↑ before RCLK↑
3
3
3
‡
5
5
5
Setup time
Hold time
t
t
ns
ns
su
SRCLR low before RCLK↑
SRCLR high (inactive) before SRCLK↑
SER after SRCLK↑
5
5
5
3.4
2
3.8
2
3.8
2
h
‡
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
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ꢤ
ꢚ
ꢛ
ꢣ
ꢦ
ꢟ
ꢧ
ꢢ
ꢥ
ꢚ
ꢜ
ꢱ
ꢣ
ꢟ
ꢧ
ꢝ
ꢨ
ꢣ
ꢠ
ꢜ
ꢦ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢝ
ꢥ
ꢧ
ꢣ
ꢞ
ꢣ
ꢝ
ꢜ
ꢯ
ꢤ
ꢯ
ꢟ
ꢥ
ꢪ
ꢝ
ꢫ
ꢇ
ꢣ
ꢬ
ꢥ
ꢝ
ꢎ
ꢤ
ꢝ
ꢚ
ꢧ
ꢡ
ꢢ
ꢣ
ꢤ
ꢚ
ꢝ
ꢧ
ꢠ ꢛ ꢥ ꢤ ꢯꢣ ꢟꢧ ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡ ꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢨꢧ ꢟ ꢞꢡꢠ ꢚꢝ ꢭ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢫ
ꢣ
ꢝ
ꢣ
ꢧ
ꢱ
ꢣ
ꢝ
ꢚ
ꢛ
ꢣ
ꢧ
ꢜ
ꢯ
ꢛ
ꢚ
ꢚ
ꢟ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢂ
ꢈ
ꢂ
ꢉ
ꢋ ꢌꢍꢎ ꢇ ꢀꢅ ꢎꢏ ꢇ ꢐꢑ ꢒ ꢎꢀ ꢇꢑ ꢐ
ꢀ
ꢁ
ꢊ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢂ
ꢈ
ꢂ
ꢀ
ꢀ
ꢓ
ꢎꢇ
ꢅ
ꢔ
ꢌ
ꢀ
ꢇ
ꢄ
ꢇ
ꢑ
ꢕ
ꢖ
ꢇ
ꢗ
ꢖꢇ
ꢐꢑ
ꢒ
ꢎꢀ
ꢇꢑ
ꢐ
SCLS374L − MAY 1997 − REVISED FEBRUARY 2004
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
170*
140
4.3*
4.3*
4.5*
4.5*
4.5*
4.3*
5.4*
5.6
SN54AHCT595 SN74AHCT595
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
135*
95
MAX
MIN
115*
85
1*
1*
1*
1*
1*
1*
1*
1
MAX
MIN
115
85
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
max
t
t
t
t
t
t
t
t
t
t
t
t
7.4*
7.4*
8.2*
8.2*
8*
8.5*
8.5*
9.4*
9.4*
9.1*
10*
8.5
8.5
PLH
PHL
PLH
PHL
PHL
PZH
PZL
PLH
PHL
PLH
PHL
PHL
C
= 15 pF
RCLK
Q −Q
A
L
H
1
1
9.4
C
C
= 15 pF
= 15 pF
ns
ns
SRCLK
SRCLR
Q
Q
L
L
H′
H′
1
9.4
1
9.1
8.6*
8.6*
9.4
1
10
C
C
= 15 pF
= 50 pF
ns
ns
OE
Q −Q
A
L
L
H
10*
1
10
10.5
10.5
11.4
11.4
11.1
1
10.5
10.5
11.4
11.4
11.1
RCLK
Q −Q
A
H
5.6
9.4
1
1
6.4
10.2
10.2
10
1
1
C
C
= 50 pF
= 50 pF
ns
ns
SRCLK
SRCLR
Q
L
L
H′
6.4
1
1
6.4
1
1
Q
H′
t
t
t
t
5.7
6.8
3.5
3.4
10.6
10.6
10.3
10.3
1
1
1
1
12
12
11
11
1
1
1
1
12
12
11
11
PZH
PZL
PHZ
PLZ
C
C
= 50 pF
= 50 pF
ns
ns
OE
OE
Q −Q
A
L
L
H
Q −Q
A
H
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
= 5 V, C = 50 pF, T = 25°C (see Note 4)
CC
L
A
SN74AHCT595
PARAMETER
UNIT
MIN
TYP
1
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
−0.6
3.8
OL
OH
2
0.8
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
112
pF
pd
ꢗ
ꢐ
ꢕ
ꢙ
ꢖ
ꢆ
ꢇ
ꢗ
ꢐ
ꢑ
ꢰ
ꢎ
ꢑ
ꢓ
ꢜ
ꢤ
ꢦ
ꢟ
ꢧ
ꢢ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢠ
ꢟ
ꢤ
ꢠ
ꢣ
ꢧ
ꢤ
ꢝ
ꢨ
ꢧ
ꢟ
ꢞ
ꢡ
ꢠ
ꢚ
ꢝ
ꢞꢣ ꢝ ꢜ ꢯꢤ ꢨꢛ ꢥ ꢝ ꢣ ꢟꢦ ꢞꢣ ꢱ ꢣ ꢪꢟ ꢨꢢꢣ ꢤꢚꢫ ꢆ ꢛꢥ ꢧꢥ ꢠꢚ ꢣꢧ ꢜꢝ ꢚꢜ ꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢧ
ꢜ
ꢤ
ꢚ
ꢛ
ꢣ
ꢦ
ꢟ
ꢧ
ꢢ
ꢥ
ꢚ
ꢜ
ꢱ
ꢣ
ꢟ
ꢧ
ꢝ
ꢨ
ꢣ
ꢠ
ꢜ
ꢦ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢝ
ꢥ
ꢧ
ꢣ
ꢞ
ꢣ
ꢝ
ꢜ
ꢯ
ꢤ
ꢯ
ꢟ
ꢥ
ꢪ
ꢝ
ꢫ
ꢇ
ꢣ
ꢬ
ꢥ
ꢝ
ꢎ
ꢤ
ꢝ
ꢚ
ꢧ
ꢡ
ꢢ
ꢣ
ꢤ
ꢚ
ꢝ
ꢧ
ꢠ ꢛꢥ ꢤ ꢯꢣ ꢟꢧ ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢨꢧ ꢟꢞ ꢡꢠꢚ ꢝ ꢭ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢫ
ꢣ
ꢝ
ꢣ
ꢧ
ꢱ
ꢣ
ꢝ
ꢚ
ꢛ
ꢣ
ꢧ
ꢜ
ꢯ
ꢛ
ꢚ
ꢚ
ꢟ
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢂꢈ ꢂꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇꢂ ꢈ ꢂ
ꢋꢌ ꢍꢎ ꢇ ꢀꢅ ꢎ ꢏ ꢇ ꢐ ꢑꢒ ꢎꢀ ꢇꢑ ꢐꢀ
ꢓꢎ ꢇ ꢅ ꢔ ꢌꢀꢇꢄꢇ ꢑ ꢕꢖꢇ ꢗ ꢖꢇ ꢐꢑ ꢒ ꢎꢀ ꢇꢑ ꢐꢀ
SCLS374L − MAY 1997 − REVISED FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
0 V
1.5 V
Timing Input
t
w
t
h
3 V
t
su
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
0 V
t
t
t
t
t
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
CC
V
V
+ 0.3 V
OL
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
− 0.3 V
OH
50% V
CC
50% V
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
SN74AHCT595D
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOIC
SSOP
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
16
16
16
16
16
16
16
16
16
16
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
AHCT595
SN74AHCT595DBR
SN74AHCT595DBRE4
SN74AHCT595DBRG4
SN74AHCT595DE4
SN74AHCT595DG4
SN74AHCT595DR
SN74AHCT595DRE4
SN74AHCT595DRG4
SN74AHCT595N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DB
DB
DB
D
2000
2000
2000
40
Green (RoHS
& no Sb/Br)
HB595
Green (RoHS
& no Sb/Br)
HB595
Green (RoHS
& no Sb/Br)
HB595
Green (RoHS
& no Sb/Br)
AHCT595
AHCT595
AHCT595
AHCT595
AHCT595
SN74AHCT595N
SN74AHCT595N
AHCT595
D
40
Green (RoHS
& no Sb/Br)
D
2500
2500
2500
25
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
N
Pb-Free
(RoHS)
SN74AHCT595NE4
N
25
Pb-Free
(RoHS)
N / A for Pkg Type
SN74AHCT595NSR
SN74AHCT595NSRE4
SN74AHCT595NSRG4
SN74AHCT595PW
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
SO
SO
NS
NS
NS
PW
16
16
16
16
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
-40 to 85
-40 to 85
SO
Call TI
Call TI
TSSOP
90
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
HB595
HB595
HB595
HB595
SN74AHCT595PWE4
SN74AHCT595PWG4
SN74AHCT595PWR
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
PW
PW
PW
16
16
16
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
90
Green (RoHS
& no Sb/Br)
2000
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
SN74AHCT595PWRE4
SN74AHCT595PWRG4
ACTIVE
TSSOP
TSSOP
PW
16
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
HB595
HB595
ACTIVE
PW
2000
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AHCT595DBR
SN74AHCT595DR
SN74AHCT595PWR
SSOP
SOIC
DB
D
16
16
16
2000
2500
2000
330.0
330.0
330.0
16.4
16.4
12.4
8.2
6.5
6.9
6.6
10.3
5.6
2.5
2.1
1.6
12.0
8.0
16.0
16.0
12.0
Q1
Q1
Q1
TSSOP
PW
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74AHCT595DBR
SN74AHCT595DR
SN74AHCT595PWR
SSOP
SOIC
DB
D
16
16
16
2000
2500
2000
367.0
333.2
367.0
367.0
345.9
367.0
38.0
28.6
35.0
TSSOP
PW
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
SN74AHCT595DG4
AHCT/VHCT/VT SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16
TI
SN74AHCT595DRG4
AHCT/VHCT/VT SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16
TI
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