SN74ALS164AD [TI]
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER; 8位并行输出串行移位寄存器
| 型号： | SN74ALS164AD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER |
| 文件： | 总6页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALS164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER
SDAS159D – APRIL 1982 – REVISED DECEMBER 1994
D OR N PACKAGE
(TOP VIEW)
• AND-Gated (Enable/Disable) Serial Inputs
• Fully Buffered Clock and Serial Inputs
• Direct Clear
• Package Options Include Plastic
Small-Outline (D) Packages and Standard
Plastic (N) 300-mil DIPs
A
B
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
Q
Q
Q
Q
CLR
CLK
H
G
F
Q
Q
Q
A
B
C
D
E
description
Q
GND
8
This 8-bit parallel-out serial shift register features
AND-gated serial (A and B) inputs and an
asynchronous clear (CLR) input. The gated serial
inputs permit control over incoming data because a low at either input inhibits entry of the new data and resets
the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which
determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low,
provided that the minimum setup-time requirements are met. Clocking occurs on the low-to-high-level transition
of the clock (CLK) input. All inputs are diode clamped to minimize transmission-line effects.
The SN74ALS164A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
†
INPUTS
OUTPUTS
CLR
L
CLK
A
X
X
H
L
B
X
X
H
X
L
Q
Q
B
. . . Q
A
H
X
L
↑
↑
↑
L
L
L
H
Q
Q
Q
H0
Q
Gn
Q
Gn
Q
Gn
A0
B0
An
An
An
H
H
L
L
Q
Q
Q
H
H
X
†
Q
, Q , Q = the level of Q , Q , or Q , respectively,
A0 B0 H0
A
B
H
before the indicated steady-state input conditions were
established.
H = high level (steady state), L = low level (steady state)
X = irrelevant (any input, including transitions)
↑ = transition from low to high level
Q
, Q = the level of Q or Q before the most recent
An Gn A G
↑ transition of the clock; indicates a 1-bit shift.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER
SDAS159D – APRIL 1982 – REVISED DECEMBER 1994
†
logic symbol
SRG8
9
R
CLR
CLK
8
C1/
&
1
2
3
A
B
Q
Q
1D
A
B
4
5
Q
Q
Q
Q
Q
Q
C
D
E
F
6
10
11
12
13
G
H
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
9
CLR
8
CLK
1
2
R
R
R
R
R
R
R
R
A
B
1R
C1
1S
1R
C1
1S
1R
C1
1S
1R
C1
1S
1R
C1
1S
1R
C1
1S
1R
C1
1S
1R
C1
1S
3
4
5
6
10
11
12
Q
13
Q
Q
Q
Q
Q
Q
Q
H
A
B
C
D
E
F
G
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER
SDAS159D – APRIL 1982 – REVISED DECEMBER 1994
typical clear, shift, and clear sequences
CLR
A
B
CLK
Q
Q
Q
Q
A
B
C
D
Q
E
Q
F
Q
G
Q
H
Clear
Clear
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER
SDAS159D – APRIL 1982 – REVISED DECEMBER 1994
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5
5.5
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
V
IH
0.8
–0.4
8
V
IL
I
I
f
mA
mA
MHz
OH
OL
clock
50
CLK
10
16
6
t
Pulse duration
ns
ns
w
CLR low
Data
t
t
Setup time before CLK↑
su
CLR inactive
8
Hold time, data after CLK↑
2
ns
h
T
A
Operating free-air temperature
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
IK
V
V
= 4.5 V,
I = –18 mA
I
–1.5
CC
V
OH
= 4.5 V to 5.5 V,
I
I
I
= –0.4 mA
= 4 mA
V –2
CC
V
CC
OH
OL
OL
0.25
0.35
0.4
0.5
V
OL
V
CC
= 4.5 V
V
= 8 mA
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 7 V
0.1
mA
µA
I
I
V = 2.7 V
I
20
IH
IL
V = 0.4 V
I
–0.1
–112
24
mA
mA
mA
‡
V
O
= 2.25 V
–30
O
See Note 1
14
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
is measured after a clock transition from
NOTE 1: With 4.5 V applied to the serial input and all other inputs, except the CLK, grounded, I
0 to 4.5 V.
CC
switching characteristics (see Figure 1)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
FROM
(INPUT)
TO
(OUTPUT)
= 500 Ω,
PARAMETER
UNIT
§
T
A
= MIN to MAX
¶
MIN TYP
MAX
f
t
t
t
50
6
75
15
9
MHz
ns
max
PHL
PLH
PHL
CLR
CLK
Any Q
Any Q
20
16
17
4
ns
5
11
§
¶
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at V = 5 V, T = 25°C.
CC
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER
SDAS159D – APRIL 1982 – REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
h
t
w
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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