SN74ALS236DWR [TI]
64X4 OTHER FIFO, 22ns, PDSO16, PLASTIC, SO-16;
| 型号： | SN74ALS236DWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 64X4 OTHER FIFO, 22ns, PDSO16, PLASTIC, SO-16 先进先出芯片 光电二极管 |
| 文件： | 总13页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALS236
64 × 4
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS107C – OCTOBER 1986 – REVISED APRIL 1998
DW OR N PACKAGE
(TOP VIEW)
Asynchronous Operation
Organized as 64 Words by 4 Bits
Data Rates up to 30 MHz
3-State Outputs
V
NC
IR
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
SO
OR
Q0
SI
D0
Package Options Include Plastic
Small-Outline Package (DW), Plastic
J-Leaded Chip Carriers (FN), and Standard
Plastic 300-mil DIPs (N)
Q1
D1
Q2
D2
Q3
D3
description
RST
GND
The SN74ALS236 is a 256-bit memory utilizing
advanced low-power Schottky IMPACT
technology. It features high speed with fast
fall-through times and is organized as 64 words by
4 bits.
FN PACKAGE
(TOP VIEW)
A first-in, first-out (FIFO) memory is a storage
device that allows data to be written into and read
from its array at independent data rates. The
SN74ALS236 is designed to process data at rates
up to 30 MHz in a bit-parallel format, word by
word.
3
2 1 20 19
SI
OR
Q0
NC
Q1
Q2
18
17
16
15
14
4
5
6
7
8
D0
NC
D1
D2
9 10 11 12 13
Data is written into memory on the rising edge of
the shift-in (SI) input. When SI goes low, the first
data word ripples through to the output (see
Figure 1). As the FIFO fills up, the data words
stack up in the order they were written. When the
FIFO is full, additional shift-in pulses have no
effect. Data is shifted out of memory on the falling
NC – No internal connection
edge of the shift-out (SO) input (see Figure 2). When the FIFO is empty, additional SO pulses have no effect.
The last data word remains at the outputs until a new word falls through or reset (RST) goes low.
Status of the SN74ALS236 FIFO memory is monitored by the output-ready (OR) and input-ready (IR) flags.
When OR is high, valid data is available at the outputs. OR is low when SO is high and stays low when the FIFO
is empty. IR is high when the inputs are ready to receive more data. IR is low when SI is high and stays low when
the FIFO is full.
When the FIFO is empty, input data is shifted to the output automatically when SI goes low. If SO is held high
during this time, the OR flag pulses high, indicating valid data at the outputs (see Figure 3).
When the FIFO is full, data is shifted in automatically by holding SI high and taking SO low. One propagation
delay after SO goes low, IR goes high. If SI is still high when IR goes high, data at the inputs is automatically
shifted in. Since IR is normally low when the FIFO is full and SI is high, only a high-level pulse is seen on the
IR output (see Figure 4).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
IMPACT is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS236
64 × 4
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS107C – OCTOBER 1986 – REVISED APRIL 1998
description (continued)
The FIFO must be reset after power up with a low-level pulse on the master reset (RST) input. This sets IR high
and OR low, signifying that the FIFO is empty. Resetting the FIFO sets the outputs to a low logic level (see
Figure 1). If SI is high when RST goes high, the input data is shifted in and IR goes low and remains low until
SI goes low. If SI goes low before RST goes high, the input data is not shifted in and IR goes high. Data outputs
are noninverting with respect to the data inputs.
The SN74ALS236 is characterized for operation from 0°C to 70°C.
†
logic symbol
FIFO 64 × 4
CTR
3
14
2
SI
5 + /C1
G2
4 –
G3
OR
IR
3CT > 0
(CT > 0) G4
15
SO
2CT < 64
(CT < 64) G5
CT = 0
R
9
RST
4
5
6
7
13
12
11
10
D0
D1
D2
D3
1D
Q0
Q1
Q2
Q3
†
This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW and N packages.
functional block diagram
4
13
D0
5
Q0
Q1
12
11
D1
D2
D3
FIFO
Input
Stage
FIFO
Output
Stage
6
7
62 × 4 Bit
Register
Q2
Q3
10
2
15
14
IR
SO
OR
Input-
Control
Logic
Register-
Control
Logic
Output-
Control
Logic
3
9
SI
RST
Pin numbers shown are for the DW and N packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
Word 64
Word 63
Word 3
Word 2
Word 1
D0
Q0
D1
D2
D3
Q1
Q2
Q3
Words 4 – 62
Same as 3 or 63
RST
SO
OR
IR
SI
SN74ALS236
64 × 4
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS107C – OCTOBER 1986 – REVISED APRIL 1998
timing diagram
RST
SI
Don’t Care
W1
W2
W1
W2
W63 W64
W1
D3–D0
SO
†
‡
Word 1
Word 2
Invalid
Word 2
Word 3
Word 1
Q3–Q0
IR
OR
Clear
Shift Out
W2
Full
Shift In
W1
Empty
†
‡
The last data word shifted out of the FIFO remains at the output until a new word falls through or an RST pulse clears the FIFO.
While the output data is considered valid only when the OR flag is high, the stored data remains at the outputs. Any additional words written
into the FIFO stack up behind the first word and do not appear at the output until SO is taken low.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS236
64 × 4
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS107C – OCTOBER 1986 – REVISED APRIL 1998
RST
SI
t
su
t
h
t
su
D3–D0
t
t
t
PHL
t
PLH
PLH
IR Full
t
PHL
PLH
Empty
OR
t
pd
t
pd
Q3–Q0
NOTE A: SO is low.
Figure 1. Master Reset and Data-In Waveforms
SO
t
PLH
OR
IR
t
PHL
t
PLH
Full
t
d(SOL-QX)
Q3–Q0
t
pd
NOTE A: SI is low.
Figure 2. Data-Out Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS236
64 × 4
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS107C – OCTOBER 1986 – REVISED APRIL 1998
D3–D0
t
su
t
h
SI
SO
OR
t
PLH
t
w
Empty
t
d(QV-ORH)
Q3–Q0
Invalid
Figure 3. Data Fall-Through Waveforms
SO
SI
IR
t
PLH
t
w
Full
Full
D3–D0
Figure 4. Automatic Data-In Waveforms
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105°C/W
JA
FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS236
64 × 4
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS107C – OCTOBER 1986 – REVISED APRIL 1998
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
V
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
0.8
– 2.6
– 0.4
24
Q outputs
IR and OR
Q outputs
IR and OR
I
High-level output current
mA
OH
OL
I
Low-level output current
mA
8
T
A
Operating free-air temperature
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
= 4.5 V,
= 4.5 V
= 4.5 V,
= 4.5 V
–1.2
V
IK
CC
CC
CC
CC
I
I
I
I
I
I
I
I
= –1 mA
= –2.6 mA
= –0.4 mA
= 12 mA
= 24 mA
= 4 mA
OH
OH
OH
OL
OL
OL
OL
Any Q
IR, OR
Any Q
V
2.4
2.7
3.2
3.4
V
V
OH
0.25
0.35
0.25
0.35
0.4
0.5
V
OL
0.4
IR, OR
V
CC
= 4.5 V
= 8 mA
0.5
I
I
I
I
V
V
V
V
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 7 V
0.1
mA
µA
I
CC
CC
CC
CC
I
V = 2.7 V
I
20
IH
IL
V = 0.4 V
I
–0.1
–112
145
142
mA
mA
‡
V
O
= 2.25 V
–30
O
Low
100
97
I
V
CC
= 5.5 V
mA
CC
High
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, I
.
OS
timing requirements over recommended operating conditions (unless otherwise noted) (see
Figure 5)
MIN
MAX
UNIT
f
t
Clock frequency
Pulse duration
SI or SO
SI or SO
RST
30
MHz
clock
High or low
Low
15
15
0
ns
w
Data
Setup time before SI↑
t
t
ns
ns
High
(inactive)
su
RST
15
17
Hold time, data after SI↑
h
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS236
64 × 4
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS107C – OCTOBER 1986 – REVISED APRIL 1998
switching characteristics (see Figure 5)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
MIN TYP
MAX
MIN
MAX
UNIT
SI
SO
35
35
15
19
6
30
30
8
f
MHz
max
‡
§
tw
IR high
ns
ns
ns
ns
tw
OR high
8
t
t
Q valid before OR↑
9
–5
12
d(QV-ORH)
Q valid after SO↓
13
4
d(SOL-QX)
t
t
t
t
t
t
t
t
t
t
t
SI↓
SI↑
Q
600
20
800
26
350
8
1000
30
ns
ns
pd
PHL
PLH
IR
SI↓
16
21
6
25
¶
SI↓
OR
Q
600
13
800
17
350
4
1000
22
ns
ns
PLH
SO↓
SO↑
SO↓
SO↓
pd
23
27
7
33
PHL
PLH
OR
ns
ns
ns
ns
20
24
6
30
¶
IR
OR
IR
600
22
800
26
350
10
6
1000
34
PLH
PHL
PLH
PHL
RST↓
RST↓
17
21
27
Q
14
14
17
5
19
†
‡
§
¶
All typical values are at V
= 5 V, T = 25°C.
A
CC
The IR output pulse occurs when the FIFO is full, SI is high, and SO is pulsed (see Figure 4).
The OR output pulse occurs when the FIFO is empty, SO is high, and SI is pulsed (see Figure 3).
Data throughput or fall-through times
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS236
64 × 4
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS107C – OCTOBER 1986 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
7 V
PARAMETER
S1
Open
S1
t
Open
PZH
t
t
t
en
dis
pd
t
Closed
Open
PZL
R1 = 500 Ω
t
PHZ
t
From Output
Under Test
Closed
PLZ
PLH
PHL
Test Point
R2 = 500 Ω
t
t
Open
Open
C
= 50 pF
L
(see Note A)
LOAD CIRCUIT FOR 3-STATE OUTPUTS
3.5 V
0.3 V
1.3 V
High-Level
Pulse
1.3 V
t
w
3.5 V
Timing
Input
3.5 V
0.3 V
1.3 V
Low-Level
Pulse
1.3 V
1.3 V
0.3 V
3.5 V
0.3 V
t
h
t
su
VOLTAGE WAVEFORMS
PULSE DURATION
Data
Input
1.3 V
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3.5 V
Output
Control
1.3 V
1.3 V
0.3 V
3.5 V
3.5 V
Input
(see Note C)
t
PZL
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
t
t
PLH
Waveform 1
S1 Closed
(see Note B)
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
V
OL
0.3 V
t
PHZ
t
t
PLH
PZH
t
V
OH
PHL
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
1.3 V
1.3 V
0.3 V
0 V
V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
o
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 5. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS236
64 × 4
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDAS107C – OCTOBER 1986 – REVISED APRIL 1998
APPLICATION INFORMATION
SO
IR
SO
OR
Q0
Q1
Q2
Q3
IR
SO
OR
Q0
Q1
Q2
Q3
IR
SO
OR
Q0
Q1
Q2
Q3
SI
SI
SI
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
RST
RST
RST
RST
RST
RST
RST
RST
RST
IR
IR
SO
OR
Q0
Q1
Q2
Q3
IR
SO
OR
Q0
Q1
Q2
Q3
IR
SO
OR
Q0
Q1
Q2
Q3
SI
SI
SI
OR
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
IR
SO
OR
Q0
Q1
Q2
Q3
IR
SO
OR
Q0
Q1
Q2
Q3
IR
SO
OR
Q0
Q1
Q2
Q3
SI
SI
SI
SI
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
RST
Figure 6. Word-Width Expansion: 192 × 12 Bits
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
22-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74ALS236N
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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