SN74ALS240A-1NSRE4 [TI]
OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS; 八路缓冲器/驱动器，具有三态输出
| 型号： | SN74ALS240A-1NSRE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总17页 (文件大小：536K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS240A, SN54AS240A, SN74ALS240A, SN74AS240A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SDAS214E – DECEMBER 1982 – REVISED AUGUST 2002
SN54ALS240A, SN54AS240A . . . J OR W PACKAGE
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
SN74ALS240A . . . DB, DW, N, OR NS PACKAGE
SN74AS240A . . . DW OR N PACKAGE
(TOP VIEW)
pnp Inputs Reduce dc Loading
description/ordering information
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
2OE
1Y1
2A4
1Y2
2A3
1Y3
These octal buffers/drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. When these devices are used with
the ’ALS241, ’AS241A, ’ALS244, and ’AS244A
devices, the circuit designer has a choice of
selected combinations of inverting and
noninverting outputs, symmetrical active-low
output-enable (OE) inputs, and complementary
OE and OE inputs. These devices feature high
fan-out and improved fan-in.
13 2A2
12 1Y4
11
2A1
SN54ALS240A, SN54AS240A . . . FK PACKAGE
(TOP VIEW)
The -1 version of SN74ALS240A is identical to the
standard version, except that the recommended
3
2
1
20 19
18
1Y1
2A4
1Y2
2A3
1Y3
1A2
2Y3
1A3
2Y2
1A4
maximum I for the -1 version is 48 mA. There is
4
5
6
7
8
OL
no -1 version of the SN54ALS240A.
17
16
15
14
9 10 11 12 13
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
SN74ALS240AN
SN74ALS240A-1N
SN74AS240AN
SN74ALS240AN
SN74ALS240A-1N
SN74AS240AN
PDIP – N
Tube
Tube
SN74ALS240ADW
ALS240A
ALS240A-1
AS240A
Tape and reel SN74ALS240ADWR
Tube SN74ALS240A-1DW
Tape and reel SN74ALS240A-1DWR
Tube SN74AS240ADW
SOIC – DW
0°C to 70°C
Tape and reel SN74AS240ADWR
SN74ALS240ANSR
Tape and reel
ALS240A
ALS240A-1
G240A
SOP – NS
SN74ALS240A-1NSR
SN74ALS240ADBR
Tape and reel
SSOP – DB
SN74ALS240A-1DBR
G240A-1
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS240A, SN54AS240A, SN74ALS240A, SN74AS240A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SDAS214E – DECEMBER 1982 – REVISED AUGUST 2002
description/ordering information (continued)
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
†
PACKAGE
T
A
PART NUMBER
SNJ54ALS240AJ
SNJ54AS240AJ
SNJ54ALS240AJ
SNJ54AS240AJ
SNJ54ALS240AW
SNJ54AS240AW
SNJ54ALS240AFK
SNJ54AS240AFK
CDIP – J
CFP – W
LCCC – FK
Tube
Tube
Tube
SNJ54ALS240AW
SNJ54AS240AW
SNJ54ALS240AFK
SNJ54AS240AFK
–55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
L
H
Z
H
X
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS240A, SN54AS240A, SN74ALS240A, SN74AS240A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SDAS214E – DECEMBER 1982 – REVISED AUGUST 2002
logic diagram (positive logic)
1
1OE
18
16
2
4
1Y1
1Y2
1Y3
1Y4
1A1
1A2
14
12
6
8
1A3
1A4
19
2OE
9
7
11
13
2Y1
2Y2
2A1
2A2
2A3
2A4
5
3
15
17
2Y3
2Y4
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θ (see Note 1): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS240A, SN54AS240A, SN74ALS240A, SN74AS240A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SDAS214E – DECEMBER 1982 – REVISED AUGUST 2002
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
CC
High-level input voltage
V
IH
SN54ALS240A
0.7
0.8
–12
–15
12
V
Low-level input voltage
High-level output current
V
IL
SN74ALS240A, ’AS240A
SN54ALS240A, SN54AS240A
SN74ALS240A, SN74AS240A
SN54ALS240A
I
mA
OH
24
SN74ALS240A
†
48
I
Low-level output current
mA
OL
SN54AS240A
48
64
SN74AS240A
SN54ALS240A, SN54AS240A
SN74ALS240A, SN74AS240A
–55
125
70
T
A
Operating free-air temperature
°C
0
†
Applies only to the -1 version and only if V
CC
is between 4.75 V and 5.25 V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS240A
SN74ALS240A
PARAMETER
TEST CONDITIONS
UNIT
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
I
I
I
I
= –0.4 mA
= –3 mA
= –12 mA
= –15 mA
= 12 mA
V
–2
V
–2
CC
OH
OH
OH
OH
OL
OL
OL
CC
2.4
CC
2.4
3.2
3.2
V
OH
V
V
= 4.5 V
= 4.5 V
2
CC
CC
2
0.25
0.4
0.25
0.35
0.35
0.4
0.5
0.5
20
V
OL
V
= 24 mA
V
†
= 48 mA
= 2.7 V
= 0.4 V
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
20
–20
0.1
µA
µA
OZH
OZL
I
O
O
V
–20
0.1
20
V = 7 V
I
mA
µA
V = 2.7 V
I
20
IH
V = 0.4 V
I
–0.1
–112
11
–0.1
–112
11
mA
mA
IL
§
V
O
= 2.25 V
–20
–30
O
Outputs high
Outputs low
4
13
14
4
13
14
I
V
CC
= 5.5 V
23
23
mA
CC
Outputs disabled
25
25
†
‡
§
Applies only to the -1 version and only if V
CC
is between 4.75 V and 5.25 V
= 5 V, T = 25°C.
All typical values are at V
CC
A
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, I
.
OS
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS240A, SN54AS240A, SN74ALS240A, SN74AS240A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SDAS214E – DECEMBER 1982 – REVISED AUGUST 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS240A
SN74AS240A
PARAMETER
TEST CONDITIONS
I = –18 mA
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
–1.2
–1.2
V
IK
CC
I
I
I
I
I
I
I
= –2 mA
= –3 mA
= –12 mA
= –15 mA
= 48 mA
= 64 mA
= 2.7 V
V
–2
V
–2
OH
OH
OH
OH
OL
OL
CC
2.4
CC
2.4
= 4.5 V to 5.5 V
CC
3.4
3.4
V
OH
2.4
V
V
= 4.5 V
= 4.5 V
CC
2.4
0.27
0.55
V
OL
V
CC
0.31
0.55
50
I
I
I
I
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
50
–50
0.1
µA
µA
mA
µA
OZH
OZL
I
O
O
V
= 0.4 V
–50
0.1
20
V = 7 V
I
V = 2.7 V
I
20
IH
A inputs
–1
–1
I
V
= 5.5 V,
= 5.5 V,
V = 0.4 V
mA
mA
IL
CC
CC
I
OE inputs
–0.5
–150
17
–0.5
–150
17
‡
I
O
V
V
O
= 2.25 V
–50
–50
Outputs high
Outputs low
11
51
24
11
51
24
I
V
CC
= 5.5 V
75
75
mA
CC
Outputs disabled
38
38
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, I
.
OS
switching characteristics (see Figure 1)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
R1 = 500 Ω,
R2 = 500 Ω,
T
A
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
UNIT
§
= MIN to MAX
SN54ALS240A SN74ALS240A
MIN
2
MAX
22
MIN
2
MAX
9
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
A
ns
ns
ns
Y
Y
Y
2
11
2
9
4
34
5
13
18
10
12
OE
OE
5
26
5
1
15
2
3
24
3
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS240A, SN54AS240A, SN74ALS240A, SN74AS240A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SDAS214E – DECEMBER 1982 – REVISED AUGUST 2002
switching characteristics (see Figure 1)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
R1 = 500 Ω,
R2 = 500 Ω,
T
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
†
= MIN to MAX
SN54AS240A
SN74AS240A
MIN
1
MAX
7
MIN
1
MAX
6.5
6.5
6.4
9
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
A
ns
ns
ns
Y
Y
Y
1.2
1
6.5
7
1.2
1
OE
OE
1.1
1.2
1.5
9.5
5.5
12.5
1.1
1.2
1.5
5
9.5
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS240A, SN54AS240A, SN74ALS240A, SN74AS240A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SDAS214E – DECEMBER 1982 – REVISED AUGUST 2002
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
t
w
h
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
≈3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
V
OL
0.3 V
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
0.3 V
≈0 V
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
17-Oct-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-8859101SA
JM38510/38301B2A
JM38510/38301BRA
SN54ALS240AJ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CFP
W
FK
J
20
20
20
20
20
20
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
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Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
LCCC
CDIP
CDIP
CDIP
SSOP
J
SN54AS240AJ
J
SN74ALS240A-1DBR
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS240A-1DBRE4
SN74ALS240A-1DW
SN74ALS240A-1DWE4
SN74ALS240A-1DWR
SN74ALS240A-1DWRE4
SN74ALS240A-1N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
DB
DW
DW
DW
DW
N
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74ALS240A-1NE4
SN74ALS240A-1NSR
SN74ALS240A-1NSRE4
SN74ALS240ADW
N
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
NS
NS
DW
DW
DW
DW
N
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS240ADWE4
SN74ALS240ADWR
SN74ALS240ADWRE4
SN74ALS240AN
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74ALS240ANE4
SN74ALS240ANSR
SN74ALS240ANSRE4
SN74AS240ADW
N
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
NS
NS
DW
DW
DW
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AS240ADWE4
SN74AS240ADWR
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AS240ADWRE4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Oct-2005
Orderable Device
SN74AS240AN
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PDIP
N
20
20
20
20
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74AS240ANE4
SN74AS240ANSR
SN74AS240ANSRE4
PDIP
SO
N
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
NS
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54ALS240AFK
SNJ54ALS240AJ
SNJ54ALS240AW
SNJ54AS240AFK
SNJ54AS240AJ
SNJ54AS240AW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
20
20
20
20
20
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
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Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
FK
J
LCCC
CDIP
CFP
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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