SN74ALS299 [TI]
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS; 8位通用移位/存储寄存器具有三态输出
| 型号： | SN74ALS299 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS |
| 文件： | 总7页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS299, SN74ALS299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDAS220B – DECEMBER 1982 – REVISED DECEMBER 1994
SN54ALS299 . . . J PACKAGE
SN74ALS299 . . . DW OR N PACKAGE
(TOP VIEW)
• Multiplexed I/O Ports Provide Improved Bit
Density
• Four Modes of Operation:
– Hold (Store)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
S0
OE1
OE2
V
CC
S1
– Shift Right
– Shift Left
– Load Data
SL
G/Q
Q
H′
G
• Operate With Outputs Enabled or at High
E/Q
H/Q
E
H
Impedance
C/Q
F/Q
C
F
• 3-State Outputs Drive Bus Lines Directly
• Can Be Cascaded for n-Bit Word Lengths
• Direct Overriding Clear
A/Q
Q
D/Q
B/Q
A
D
A′
B
CLR
GND
CLK
SR
• Applications:
– Stacked or Push-Down Registers
– Buffer Storage
SN54ALS299 . . . FK PACKAGE
(TOP VIEW)
– Accumulator Registers
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
3
2
1
20 19
18
4
5
6
7
8
G/Q
SL
G
17
16
15
14
E/Q
Q
E
C
H′
description
C/Q
A/Q
H/Q
H
F/Q
A
F
These 8-bit universal shift/storage registers
feature multiplexed I/O ports to achieve full 8-bit
data handling in a single 20-pin package. Two
function-select (S0, S1) inputs and two output-
enable (OE1, OE2) inputs can be used to choose
the modes of operation listed in the function table.
Q
D/Q
D
A′
9 10 11 12 13
Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs
in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading
out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs
asynchronously when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs, but has
no effect on clearing, shifting, or storing data.
The SN54ALS299 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ALS299 is characterized for operation from 0°C to 70°C.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS299, SN74ALS299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDAS220B – DECEMBER 1982 – REVISED DECEMBER 1994
FUNCTION TABLE
INPUTS
I/O PORTS
OUTPUTS
MODE
†
†
CLR S1 S0 OE1
OE2
CLK SL SR A/Q
B/Q
C/Q
D/Q
E/Q
F/Q
G/Q
H/Q
Q
Q
H′
A
B
C
D
E
F
G
H
A′
L
L
L
X
L
H
L
X
H
L
L
X
L
L
X
X
X
X
X
X
X
X
X
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
L
L
L
L
Clear
Hold
H
H
L
X
L
X
L
L
L
L
X
L
X
X
X
X
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
A0
A0
B0
B0
C0
C0
D0
D0
E0
E0
F0
F0
G0
G0
H0
H0
A0
A0
H0
H0
Shift
Right
H
H
L
L
H
H
L
L
L
L
↑
↑
X
X
H
L
H
L
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
H
L
Q
Q
An
An
Bn
Bn
Cn
Cn
Dn
Dn
En
En
Fn
Fn
Gn
Gn
Gn
Gn
Shift
Left
H
H
H
H
L
L
L
L
L
L
↑
↑
H
L
X
X
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
H
L
Q
Q
H
L
Bn
Bn
Cn
Cn
Dn
Dn
En
En
Fn
Fn
Gn
Gn
Hn
Hn
Bn
Bn
Load
H
H
H
X
X
↑
X
X
a
b
c
d
e
f
g
h
a
h
NOTE: a . . . h=thelevelofthesteady-stateinputatinputsAthroughH,respectively.Thisdataisloadedintotheflip-flopswhiletheflip-flopoutputs
are isolated from the I/O terminals.
†
When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequential operation
or clearing of the register is not affected.
‡
logic symbol
9
2
3
SRG8
R
CLR
OE1
OE2
S0
&
3EN13
0
1
0
1
19
12
M
3
S1
CLK
C4/1→/2←
11
7
8
SR
1,4D
3,4D
Q
A′
A/Q
A
B
Z5
Z6
5, 13
3,4D
6, 13
13
B/Q
6
C/Q
D/Q
C
D
14
5
E/Q
E
15
4
F/Q
F
G/Q
G
16
H/Q
3,4D
12, 13
2,4D
H
Z12
18
17
SL
Q
H′
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS299, SN74ALS299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDAS220B – DECEMBER 1982 – REVISED DECEMBER 1994
logic diagram (positive logic)
1
S0
19
S1
18
SL
(shift left
serial input)
11
SR
(shift right
serial input)
Six
Identical
Channels
Not
†
Shown
12
CLK
1D
C1
1D
C1
R
R
8
17
Q
Q
H′
A′
9
CLR
2
3
OE1
OE2
7
16
H/Q
A/Q
A
H
†
I/O ports not shown: B/Q (13), C/Q (6), D/Q (14), E/Q (5), F/Q (15), and G/Q (4).
B
C
D
E
F
G
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V : All inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, T : SN54ALS299 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74ALS299 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS299, SN74ALS299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDAS220B – DECEMBER 1982 – REVISED DECEMBER 1994
recommended operating conditions
SN54ALS299
MIN NOM MAX
SN74ALS299
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
0.7
–0.4
–1
0.8
–0.4
–2.6
8
Q
Q
Q
Q
or Q
A′
A
H′
H′
I
High-level output current
mA
OH
OL
– Q
H
or Q
4
A′
A
I
Low-level output current
mA
– Q
12
24
H
T
A
Operating free-air temperature
–55
125
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS299
SN74ALS299
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.5
–1.5
V
IK
CC
I
All outputs
= 4.5 V to 5.5 V,
I
I
I
I
I
I
I
= – 0.4 mA
= – 1 mA
= – 2.6 mA
= 4 mA
V
–2
CC
2.4
V
–2
CC
OH
OH
OH
OL
OL
OL
OL
CC
3.3
0.25
0.25
V
OH
Q
Q
Q
– Q
V
CC
V
CC
V
CC
= 4.5 V
= 4.5 V
= 4.5 V
A
H
2.4
3.2
0.25
0.35
0.25
0.35
0.4
0.4
0.4
0.5
or Q
A′
A
H′
= 8 mA
V
OL
V
= 12 mA
= 24 mA
0.4
– Q
H
0.5
A – H
V = 5.5 V
0.1
0.1
0.1
I
I
I
I
V
V
V
= 5.5 V
= 5.5 V,
= 5.5 V,
mA
µA
I
CC
CC
CC
Any others
V = 7 V
I
0.1
‡
V = 2.7 V
I
20
20
IH
S0, S1, SR, SL
Any others
–0.2
–0.1
–70
–112
28
–0.2
–0.1
–70
–112
28
‡
V = 0.4 V
I
mA
IL
Q
Q
or Q
–15
–20
–15
–30
A′
H′
§
V
CC
V
CC
= 5.5 V,
= 5.5 V
V
O
= 2.25 V
mA
mA
I
I
O
– Q
A
H
Outputs high
Outputs low
15
22
23
15
22
23
38
38
CC
Outputs disabled
40
40
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
For I/O ports (Q –Q ), the parameters I and I include the off-state output current.
A
H
IH
IL
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS299, SN74ALS299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDAS220B – DECEMBER 1982 – REVISED DECEMBER 1994
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN54ALS299 SN74ALS299
UNIT
MIN
MAX
MIN
MAX
f
t
Clock frequency (at 50% duty cycle)
Pulse duration
0
17
0
30
MHz
ns
clock
CLK high or low
CLR low
22
12
25
18
15
15
0
16.5
10
20
16
6
w
S0 or S1
High
Low
Setup time before CLK↑
Serial or parallel data
t
t
ns
ns
su
†
CLR
15
0
Inactive-state setup time before CLK↑
Hold time after CLK↑
S0 or S1
h
0
0
Serial or parallel data
†
Inactive-state setup time is also referred to as recovery time.
switching characteristics (see Figure 1)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
R1 = 500 Ω,
R2 = 500 Ω,
T
A
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
UNIT
‡
= MIN to MAX
SN54ALS299 SN74ALS299
MIN
17
2
MAX
MIN
30
4
MAX
f
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
19
25
21
25
29
29
22
27
27
26
15
38
16
34
13
19
15
18
22
22
16
22
17
22
8
CLK
CLK
CLR
Q –Q
A H
4
7
2
5
ns
ns
ns
ns
ns
ns
Q
or Q
A′
A′
H′
H′
4
8
6
6
Q
–Q
A
H
t
PHL
6
6
Q
or Q
t
t
t
t
t
t
t
t
5
6
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
OE1, OE2
S0, S1
Q
–Q
–Q
–Q
–Q
A
A
A
A
H
6
8
5
7
Q
Q
Q
H
H
H
6
8
1
1
OE1, OE2
S0, S1
4
5
15
12
25
1
1
4
8
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS299, SN74ALS299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDAS220B – DECEMBER 1982 – REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
h
t
w
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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