SN74ALS38BDG4 [TI]
Quad 2-input positive-NAND buffers with open collector outputs 14-SOIC 0 to 70;
| 型号： | SN74ALS38BDG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Quad 2-input positive-NAND buffers with open collector outputs 14-SOIC 0 to 70 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总18页 (文件大小：1118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS38B, SN74ALS38B
QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS
WITH OPEN-COLLECTOR OUTPUTS
SDAS196B – APRIL 1982 – REVISED DECEMBER 1994
SN54ALS38B . . . J PACKAGE
SN74ALS38B . . . D OR N PACKAGE
(TOP VIEW)
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
1A
1B
1Y
2A
2B
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
4B
4A
4Y
3B
3A
3Y
description
These devices contain four independent 2-input
positive-NAND buffers with open-collector
outputs. They perform the Boolean functions
Y = A • B or Y = A + B in positive logic. The
open-collector outputs require pullup resistors to
perform correctly. These outputs may be
connected to other open-collector outputs to
implement active-low wired-OR or active-high
wired-AND functions. Open-collector devices
2Y
GND
8
SN54ALS38B . . . FK PACKAGE
(TOP VIEW)
often are used to generate higher V
levels.
OH
3
2
1
20 19
18
The SN54ALS38B is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ALS38B is characterized for
operation from 0°C to 70°C.
1Y
NC
2A
4A
4
5
6
7
8
NC
17
16 4Y
15
14
NC
2B
NC
3B
FUNCTION TABLE
(each gate)
9 10 11 12 13
INPUTS
OUTPUT
Y
A
B
H
X
L
NC – No internal connection
H
L
L
H
H
X
†
logic symbol
logic diagram (positive logic)
1
1A
2
1
&
3
6
3
6
1A
2
1Y
2Y
3Y
4Y
1Y
2Y
3Y
4Y
1B
4
1B
4
2A
5
2A
5
2B
9
2B
3A
10
3B
12
4A
13
4B
9
3A
8
8
10
3B
11
12
4A
11
13
4B
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS38B, SN74ALS38B
QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS
WITH OPEN-COLLECTOR OUTPUTS
SDAS196B – APRIL 1982 – REVISED DECEMBER 1994
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T : SN54ALS38B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74ALS38B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS38B
MIN NOM MAX
SN74ALS38B
MIN NOM MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output current
Operating free-air temperature
IH
0.7
5.5
12
0.8
5.5
24
V
IL
V
OH
I
mA
°C
OL
T
A
–55
125
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS38B
SN74ALS38B
PARAMETER
TEST CONDITIONS
UNIT
V
‡
‡
MIN TYP
MAX
–1.5
0.4
MIN TYP
MAX
–1.5
0.4
V
V
V
V
= 4.5 V,
= 4.5 V
I = –18 mA
I
IK
CC
I
= 12 mA
= 24 mA
0.25
0.25
0.35
OL
OL
V
OL
CC
I
0.5
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
V = 7 V
0.1
20
0.1
mA
µA
I
I
V = 2.7 V
I
20
IH
V = 0.4 V
I
–0.1
0.1
–0.1
0.1
mA
mA
mA
mA
IL
V
= 5.5 V
OH
CCH
CCL
OH
V = 0
0.86
4.8
1.6
0.86
4.8
1.6
I
V = 4.5 V
I
7.8
7.8
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
switching characteristics (see Figure 1)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
= MIN to MAX
FROM
TO
(OUTPUT)
§
PARAMETER
(INPUT)
UNIT
T
A
SN54ALS38B SN74ALS38B
MIN
7
MAX
59
MIN
10
1
MAX
33
t
t
PLH
A or B
Y
ns
2
20
12
PHL
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS38B, SN74ALS38B
QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS
WITH OPEN-COLLECTOR OUTPUTS
SDAS196B – APRIL 1982 – REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
h
t
w
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
5962-86871012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
86871012A
SNJ54
ALS38BFK
5962-8687101CA
5962-8687101DA
SN74ALS38BD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
CFP
J
W
D
14
14
14
14
14
14
14
14
14
14
20
1
1
TBD
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
N / A for Pkg Type
-55 to 125
-55 to 125
0 to 70
5962-8687101CA
SNJ54ALS38BJ
A42
5962-8687101DA
SNJ54ALS38BW
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
POST-PLATE
ALS38B
SN74ALS38BDG4
SN74ALS38BDR
SN74ALS38BDRE4
SN74ALS38BDRG4
SN74ALS38BN
D
50
Green (RoHS
& no Sb/Br)
0 to 70
ALS38B
D
2500
2500
2500
25
Green (RoHS
& no Sb/Br)
0 to 70
ALS38B
D
Green (RoHS
& no Sb/Br)
0 to 70
ALS38B
D
Green (RoHS
& no Sb/Br)
0 to 70
ALS38B
N
Pb-Free
(RoHS)
0 to 70
SN74ALS38BN
SN74ALS38BN
ALS38B
SN74ALS38BNE4
SN74ALS38BNSR
SNJ54ALS38BFK
N
25
Pb-Free
(RoHS)
0 to 70
NS
FK
2000
1
Green (RoHS
& no Sb/Br)
0 to 70
LCCC
TBD
-55 to 125
5962-
86871012A
SNJ54
ALS38BFK
SNJ54ALS38BJ
SNJ54ALS38BW
ACTIVE
ACTIVE
CDIP
CFP
J
14
14
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-8687101CA
SNJ54ALS38BJ
W
5962-8687101DA
SNJ54ALS38BW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ALS38B, SN74ALS38B :
Catalog: SN74ALS38B
•
Military: SN54ALS38B
•
NOTE: Qualified Version Definitions:
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
Catalog - TI's standard catalog product
•
•
Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ALS38BDR
SN74ALS38BNSR
SOIC
SO
D
14
14
2500
2000
330.0
330.0
16.4
16.4
6.5
8.2
9.0
2.1
2.5
8.0
16.0
16.0
Q1
Q1
NS
10.5
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74ALS38BDR
SN74ALS38BNSR
SOIC
SO
D
14
14
2500
2000
367.0
367.0
367.0
367.0
38.0
38.0
NS
Pack Materials-Page 2
PACKAGE OUTLINE
J0014A
CDIP - 5.08 mm max height
S
C
A
L
E
0
.
9
0
0
CERAMIC DUAL IN LINE PACKAGE
4X .005 MIN
[0.13]
PIN 1 ID
(OPTIONAL)
A
.015-.060 TYP
[0.38-1.52]
1
14
12X .100
[2.54]
14X .014-.026
[0.36-0.66]
14X .045-.065
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
8
7
B
.245-.283
[6.22-7.19]
.2 MAX TYP
[5.08]
.13 MIN TYP
[3.3]
SEATING PLANE
C
.308-.314
[7.83-7.97]
AT GAGE PLANE
.015 GAGE PLANE
[0.38]
0 -15
TYP
14X .008-.014
[0.2-0.36]
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62]
SEE DETAIL B
14
SEE DETAIL A
1
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
8
7
SYMM
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
.002 MAX
[0.05]
ALL AROUND
(.063)
[1.6]
METAL
(
.063)
[1.6]
SOLDER MASK
OPENING
METAL
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
(R.002 ) TYP
[0.05]
DETAIL A
DETAIL B
SCALE: 15X
13X, SCALE: 15X
4214771/A 05/2017
www.ti.com
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and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
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