SN74ALS561ANE4 [TI]
SYNCHRONOUS 4-BIT COUNTERS;
| 型号： | SN74ALS561ANE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SYNCHRONOUS 4-BIT COUNTERS 输入元件 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总9页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS561A, SN74ALS561A
SYNCHRONOUS 4-BIT COUNTERS
WITH 3-STATE OUTPUTS
SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995
SN54ALS561A . . . J PACKAGE
SN74ALS561A . . . DW OR N PACKAGE
(TOP VIEW)
• Carry Output for n-Bit Cascading
• Buffer-Type Outputs Drive Bus Lines
Directly
• Choice of Asynchronous or Synchronous
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
ALOAD
CLK
A
V
CC
Clearing and Loading
RCO
CCO
OE
• Internal Look-Ahead Circuitry for Fast
B
C
D
Cascading
Q
Q
Q
Q
A
B
C
D
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
ENP
ACLR
SCLR
GND
ENT
SLOAD
description
These binary counters are programmable and
offer synchronous and asynchronous clearing as
well as synchronous and asynchronous loading.
All synchronous functions are executed on the
positive-going edge of the clock.
SN54ALS561A . . . FK PACKAGE
(TOP VIEW)
The clear function is initiated by applying a low
level to either asynchronous clear (ACLR) or
synchronous clear (SCLR). ACLR (direct clear)
overrides all other functions of the device, while
SCLR overrides only the other synchronous
functions. Data is loaded from the A, B, C, and D
inputs by applying a low level to asynchronous
load (ALOAD) or by the combination of a low level
3
2
1
20 19
18
4
5
6
7
8
B
C
CCO
OE
17
16
15
14
D
Q
Q
Q
A
B
C
ENP
ACLR
9 10 11 12 13
at synchronous load (SLOAD) and
a
positive-going clock transition. The counting
function is enabled only when enable P (ENP),
enable T (ENT), ACLR, ALOAD, SCLR, and
SLOAD are all high.
A high level at the output-enable (OE) input forces the Q outputs into the high-impedance state, and a low level
enables those outputs. Counting is independent of OE. ENT is fed forward to enable the ripple-carry output
(RCO) to produce a high-level pulse while the count is maximum (15). The clocked carry output (CCO) produces
a high-level pulse for a duration equal to that of the low level of the clock when RCO is high and the counter is
enabled (ENP and ENT are high); otherwise, CCO is low. CCO does not have the glitches commonly associated
with a ripple-carry output. Cascading is normally accomplished by connecting RCO or CCO of the first counter
to ENT of the next counter. However, for very high-speed counting, RCO should be used for cascading because
CCO does not become active until the clock returns to the low level.
The SN54ALS561A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ALS561A is characterized for operation from 0°C to 70°C.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS561A, SN74ALS561A
SYNCHRONOUS 4-BIT COUNTERS
WITH 3-STATE OUTPUTS
SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995
FUNCTION TABLE
INPUTS
ACLR ALOAD SCLR SLOAD
OPERATION
OE
H
L
ENT
X
ENP
X
CLK
X
X
L
X
X
L
X
X
X
L
X
X
X
X
L
Q outputs disabled
Asynchronous clear
Asynchronous load
Synchronous clear
Synchronous load
Count
X
X
X
L
H
H
H
H
H
H
X
X
X
L
H
H
H
H
H
X
X
↑
L
H
H
H
H
X
X
↑
L
H
H
H
H
H
↑
L
L
X
X
Inhibit counting
Inhibit counting
L
X
L
X
†
logic symbol
17
12
7
CTRDIV16
EN10
G1
OE
ENT
ENP
G2
9
6CT=0 [SYNC CLR]
M3 [COUNT]
SCLR
11
2
M4 [SYNC LOAD]
M5 [COUNT]
SLOAD
CLK
C6/1, 2, 3, 5+
Z7
8
1
18
CT=0
7, 1, 2, 9
CCO
19
ACLR
1 (CT=15) G9
RCO
C8
ALOAD
3
4
5
6
16
Q
A
A
B
C
D
4,6D/8D
10
15
Q
B
14
Q
C
13
Q
D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS561A, SN74ALS561A
SYNCHRONOUS 4-BIT COUNTERS
WITH 3-STATE OUTPUTS
SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995
logic diagram (positive logic)
17
OE
12
ENT
7
ENP
18
CCO
9
SCLR
11
19
SLOAD
RCO
2
CLK
8
ACLR
1
ALOAD
3
A
R
S
C1
16
1D
Q
A
4
B
R
S
C1
15
1D
Q
B
5
C
R
S
C1
14
1D
Q
C
6
D
R
S
C1
13
1D
Q
D
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS561A, SN74ALS561A
SYNCHRONOUS 4-BIT COUNTERS
WITH 3-STATE OUTPUTS
SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995
typical load, count, and inhibit sequences
OE
ACLR
SCLR
ALOAD
SLOAD
Don’t Care
Don’t Care
ENP
ENT
CLK
A
Don’t Care
Don’t Care
Don’t Care
Don’t Care
B
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Hi-Z
C
D
Q
A
Hi-Z
Hi-Z
Hi-Z
Q
Q
B
C
Q
D
RCO
CCO
12 13 14 15
0
1
13
14 15
0
1
5
Hi-Z
Inhibit Counting
Async
Clear
Async
Load
Sync
Clear
Sync
Load
Continue Counting
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS561A, SN74ALS561A
SYNCHRONOUS 4-BIT COUNTERS
WITH 3-STATE OUTPUTS
SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T : SN54ALS561A . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74ALS561A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS561A
MIN NOM MAX
SN74ALS561A
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
0.7
–1
0.8
–2.6
–0.4
24
Q outputs
I
High-level output current
mA
OH
CCO and RCO
Q outputs
–0.4
12
I
f
Low-level output current
Clock frequency
mA
OL
CCO and RCO
4
8
0
20
20
25
25
25
25
21
35
20
35
12
0
20
0
15
16.5
16.5
20
20
20
15
30
15
30
10
0
30
MHz
clock
ACLR or ALOAD low
CLK high
t
w
Pulse duration
ns
ns
CLK low
High
Low
ENP, ENT
Data at A, B, C, D
SCLR
Low
t
t
Setup time before CLK↑
su
High (inactive)
Low
SLOAD
High (inactive)
ACLR or ALOAD inactive
Hold time after CLK↑ for data, ENP, ENT, SCLR, or SLOAD
ns
h
T
A
Operating free-air temperature
–55
125
0
70
°C
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS561A, SN74ALS561A
SYNCHRONOUS 4-BIT COUNTERS
WITH 3-STATE OUTPUTS
SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS561A
SN74ALS561A
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.5
–1.5
V
IK
CC
I
All outputs
Q outputs
= 4.5 V to 5.5 V,
I
I
I
I
I
I
I
= –0.4 mA
= –1 mA
= –2.6 mA
= 12 mA
= 24 mA
= 4 mA
V
–2
V
CC
–2
CC
OH
OH
OH
OL
OL
OL
OL
CC
2.4
3.3
0.25
0.25
V
OH
V
CC
V
CC
V
CC
= 4.5 V
= 4.5 V
= 4.5 V
2.4
3.2
0.25
0.35
0.25
0.35
0.4
0.4
0.4
0.5
0.4
0.5
20
Q outputs
V
OL
V
CCO and RCO
= 8 mA
I
I
V
V
= 5.5 V,
= 5.5 V,
V
= 2.7 V
20
–20
0.2
µA
µA
OZH
CC
O
O
V
= 0.4 V
–20
0.2
0.1
40
OZL
CC
ENP and ENT
Other inputs
ENP and ENT
Other inputs
I
I
V
CC
= 5.5 V,
V = 7 V
I
mA
0.1
40
I
I
I
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 2.7 V
I
µA
mA
mA
IH
20
20
V = 0.4 V
I
–0.2
–70
–112
27
–0.2
–70
–112
27
IL
CCO and RCO
Q
–15
–20
–15
–30
‡
V
O
= 2.25 V
O
Outputs high
Outputs low
17
21
22
17
21
22
I
V
CC
= 5.5 V
33
33
mA
CC
Outputs disabled
36
36
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS561A, SN74ALS561A
SYNCHRONOUS 4-BIT COUNTERS
WITH 3-STATE OUTPUTS
SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995
switching characteristics (see Figure 1)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
R1 = 500 Ω,
R2 = 500 Ω,
T
A
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
UNIT
†
= MIN to MAX
SN54ALS561A SN74ALS561A
MIN
20
4
MAX
MIN
30
4
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PHL
PZH
PZL
PHZ
PLZ
15
21
35
29
35
20
38
27
50
35
65
42
35
27
20
18
35
15
22
14
28
24
28
12
20
12
18
29
24
26
16
35
23
40
30
55
33
30
22
16
14
32
12
18
12
22
19
23
10
15
CLK
CLK
Any Q
RCO
CCO
Any Q
RCO
CCO
Any Q
RCO
CCO
5
5
9
9
ns
ns
ns
ns
ns
ns
ns
ns
8
8
8
8
CLK
5
5
10
7
10
7
ALOAD
ALOAD
ALOAD
A, B, C, or D
ENT
15
12
25
12
8
15
12
25
12
8
7
7
5
5
4
4
12
4
12
4
ENT
5
5
CCO
Any Q
Any Q
ns
ns
ns
ENP
ACLR
OE
4
4
7
7
5
5
8
8
2
2
Any Q
ns
OE
2
4
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS561A, SN74ALS561A
SYNCHRONOUS 4-BIT COUNTERS
WITH 3-STATE OUTPUTS
SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
h
t
w
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1998, Texas Instruments Incorporated
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