SN74ALS564BNSR [TI]

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS;


型号：	SN74ALS564BNSR
厂家：	TEXAS INSTRUMENTS
描述：	OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS 驱动光电二极管输出元件逻辑集成电路触发器
文件：	总5页 (文件大小：85K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN54ALS564B, SN74ALS564B

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

WITH 3-STATE OUTPUTS

SDAS164B – APRIL 1982 – REVISED JANUARY 1995

SN54ALS564B . . . J OR W PACKAGE

SN74ALS564B . . . DW OR N PACKAGE

(TOP VIEW)

• 3-State Buffer-Type Inverting Outputs Drive

Bus Lines Directly

• Bus-Structured Pinout

• Buffered Control Inputs

• Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), Standard Plastic (N) and

Ceramic (J) 300-mil DIPs, and Ceramic Flat

(W) Packages

description

13 7Q

12 8Q

These octal D-type edge-triggered flip-flops

feature inverting 3-state outputs designed

specifically for bus driving. They are particularly

suitable for implementing buffer registers, I/O

ports, bidirectional bus drivers, and working

registers.

GND

CLK

SN54ALS564B . . . FK PACKAGE

(TOP VIEW)

The eight flip-flops enter data on the low-to-high

transition of the clock (CLK) input.

20 19

The output-enable (OE) input does not affect

internal operations of the flip-flops. Old data can

be retained or new data can be entered while the

outputs are in the high-impedance state.

9 10 11 12 13

The SN54ALS564B is characterized for operation

over the full military temperature range of –55°C

to 125°C. The SN74ALS564B is characterized for

operation from 0°C to 70°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

CLK

↑

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS564B, SN74ALS564B

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

WITH 3-STATE OUTPUTS

SDAS164B – APRIL 1982 – REVISED JANUARY 1995

†

logic symbol

logic diagram (positive logic)

CLK

To Seven Other Channels

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

‡

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

Operating free-air temperature range, T : SN54ALS564B . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

SN74ALS564B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

SN54ALS564B

MIN NOM MAX

SN74ALS564B

MIN NOM MAX

UNIT

Supply voltage

4.5

5.5

4.5

5.5

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Clock frequency

0.7

–1

0.8

–2.6

MHz

clock

Pulse duration, CLK high or low

Setup time, data before CLK↑

Hold time, data after CLK↑

Operating free-air temperature

–55

125

°C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS564B, SN74ALS564B

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

WITH 3-STATE OUTPUTS

SDAS164B – APRIL 1982 – REVISED JANUARY 1995

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54ALS564B

SN74ALS564B

PARAMETER

TEST CONDITIONS

UNIT

†

MIN TYP

MAX

MIN TYP

MAX

= 4.5 V,

I = –18 mA

–1.2

= 4.5 V to 5.5 V,

= –0.4 mA

= –1 mA

= –2.6 mA

= 12 mA

= 24 mA

= 2.7 V

–2

2.4

3.3

= 4.5 V

2.4

3.2

0.25

0.35

0.25

0.4

0.5

= 5.5 V,

–20

0.1

µA

OZH

OZL

= 0.4 V

–20

0.1

V = 7 V

µA

V = 2.7 V

V = 0.4 V

–0.2

–112

–0.2

–112

‡

= 2.25 V

–20

–30

Outputs high

Outputs low

= 5.5 V

Outputs disabled

†

‡

All typical values are at V

= 5 V, T = 25°C.

The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I

switching characteristics (see Figure 1)

= 4.5 V to 5.5 V,

= 50 pF,

R1 = 500 Ω,

R2 = 500 Ω,

FROM

(OUTPUT)

PARAMETER

(INPUT)

UNIT

= MIN to MAX

SN54ALS564B SN74ALS564B

MIN

MAX

MIN

MAX

MHz

max

PLH

PHL

PZH

PZL

PHZ

PLZ

CLK

Any Q

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS564B, SN74ALS564B

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

WITH 3-STATE OUTPUTS

SDAS164B – APRIL 1982 – REVISED JANUARY 1995

PARAMETER MEASUREMENT INFORMATION

SERIES 54ALS/74ALS AND 54AS/74AS DEVICES

7 V

= R1 = R2

Test

Point

From Output

Under Test

From Output

Under Test

Test

Point

Test

Point

From Output

Under Test

(see Note A)

LOAD CIRCUIT FOR

BI-STATE

TOTEM-POLE OUTPUTS

LOAD CIRCUIT

FOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

3.5 V

Timing

Input

High-Level

1.3 V

Pulse

0.3 V

3.5 V

0.3 V

Data

Input

Low-Level

1.3 V

Pulse

0.3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATIONS

3.5 V

0.3 V

Output

Control

(low-level

enabling)

1.3 V

3.5 V

PZL

Input

1.3 V

PLZ

0.3 V

PHL

3.5 V

Waveform 1

S1 Closed

(see Note B)

PLH

1.3 V

In-Phase

Output

1.3 V

0.3 V

PHZ

PLH

PZH

PHL

Waveform 2

S1 Open

(see Note B)

Out-of-Phase

Output

(see Note C)

1.3 V

0.3 V

0 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A.

C includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. When measuring propagation delay items of 3-state outputs, switch S1 is open.

D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.

E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

SN74ALS564BNSR [TI]

相关型号：

SN74ALS568A

SN74ALS568ADW

SN74ALS568ADW3

SN74ALS568ADWP3

SN74ALS568ADWR

SN74ALS568AFN

SN74ALS568AFN-00

SN74ALS568AJ4

SN74ALS568AJP4

SN74ALS568AN

SN74ALS568AN-10

SN74ALS568AN1