SN74ALS569ADWE4 [TI]
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-STATE OUTPUTS; 同步4位向上/向下十年和二进制计数器，具有三态输出
| 型号： | SN74ALS569ADWE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-STATE OUTPUTS |
| 文件： | 总23页 (文件大小：868K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
SN54ALS569A . . . J PACKAGE
SN74ALS568A, SN74ALS569A . . . DW OR N PACKAGE
(TOP VIEW)
• 3-State Q Outputs Drive Bus Lines Directly
• Counter Operation Independent of 3-State
Output
• Fully Synchronous Clear, Count, and Load
• Asynchronous Clear Is Also Provided
• Fully Cascadable
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
U/D
CLK
A
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
RCO
CCO
OE
B
C
D
Q
A
Q
B
ENP
ACLR
SCLR
GND
Q
C
Q
D
12 ENT
description
11
LOAD
The SN74ALS568A decade counter and
′ALS569A binary counters are programmable,
count up or down, and offer both synchronous and
asynchronous clearing. All synchronous functions
are executed on the positive-going edge of the
clock (CLK) input.
SN54ALS569A . . . FK PACKAGE
(TOP VIEW)
The clear function is initiated by applying a low
level to either asynchronous clear (ACLR) or
synchronousclear(SCLR). Asynchronous(direct)
clearing overrides all other functions of the device,
while synchronous clearing overrides only the
other synchronous functions. Data is loaded from
the A, B, C, and D inputs by holding load (LOAD)
low during a positive-going clock transition. The
counting function is enabled only when enable P
(ENP) and enable T (ENT) are low and ACLR,
SCLR, and LOAD are high. The up/down (U/D)
input controls the direction of the count. These
counters count up when U/D is high and count
down when U/D is low.
3
2
1
20 19
18
CCO
OE
B
C
4
5
6
7
8
17
16
15
14
Q
D
A
Q
B
ENP
ACLR
Q
C
9 10 11 12 13
A high level at the output-enable (OE) input forces the Q outputs into the high-impedance state, and a low level
enables those outputs. Counting is independent of OE. ENT is fed forward to enable the ripple-carry output
(RCO) to produce a low-level pulse while the count is zero (all Q outputs low) when counting down or maximum
(9 or 15) when counting up. The clocked carry output (CCO) produces a low-level pulse for a duration equal to
that of the low level of the clock when RCO is low and the counter is enabled (both ENP and ENT are low);
otherwise, CCO is high. CCO does not have the glitches commonly associated with a ripple-carry output.
Cascading is normally accomplished by connecting RCO or CCO of the first counter to ENT of the next counter.
However, for very high-speed counting, RCO should be used for cascading since CCO does not become active
until the clock returns to the low level.
The SN54ALS569A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ALS568A and SN74ALS569A are characterized for operation from 0°C to 70°C.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
FUNCTION TABLE
INPUTS
OPERATION
OE
H
L
ACLR SCLR LOAD
ENT
X
ENP
X
U/D
X
CLK
X
X
L
X
X
L
X
X
X
L
Q outputs disabled
Asynchronous clear
Synchronous clear
Load
X
X
X
X
L
H
H
H
H
H
H
X
X
X
↑
L
H
H
H
H
H
X
X
X
↑
L
H
H
H
H
L
L
H
L
↑
Count up
L
L
L
↑
Count down
L
H
X
X
X
Inhibit count
L
X
H
X
X
Inhibit count
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
†
logic symbols
SN74ALS568A
CTRDIV10
17
EN10
OE
1
M1 [UP]
U/D
M2 [DOWN]
2
CLK
C5/1,4,7,8,+/2,4,7,8–
18
19
Z6
CCO
RCO
6,7,8,9
12
7
G7
ENT
ENP
1,7 (CT=9) G9
2,7 (CT=0) G9
G8
9
SCLR
LOAD
5CT=0
11
M3 [LOAD]
M4 [COUNT]
8
CT=0
ACLR
3
4
5
6
16
15
14
13
Q
A
A
B
C
D
3,5D
10
Q
B
Q
C
Q
D
′ALS569A
CTRDIV16
17
1
EN10
OE
M1 [UP]
U/D
M2 [DOWN]
2
CLK
C5/1,4,7,8,+/2,4,7,8–
18
19
Z6
CCO
RCO
6,7,8,9
12
7
G7
ENT
ENP
1,7 (CT=15) G9
2,7 (CT=0) G9
G8
9
SCLR
LOAD
5CT=0
11
M3 [LOAD]
M4 [COUNT]
8
CT=0
ACLR
3
4
5
6
16
15
14
13
Q
A
A
B
C
D
3,5D
10
Q
B
Q
Q
C
D
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
logic diagrams (positive logic)
SN74ALS568A
17
OE
1
U/D
2
CLK
12
18
19
ENT
CCO
RCO
7
ENP
9
SCLR
11
LOAD
8
ACLR
3
A
C1
1D
R
16
Q
A
4
B
C1
1D
R
15
Q
B
5
C
C1
1D
R
14
Q
C
6
D
C1
1D
R
13
Q
D
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
logic diagrams (positive logic) (continued)
′ALS569A
17
OE
1
U/D
CLK
ENT
2
12
18
19
CCO
RCO
7
9
ENP
SCLR
11
8
LOAD
ACLR
3
A
C1
1D
R
16
Q
A
4
B
C1
1D
R
15
Q
B
5
C
C1
1D
R
14
Q
C
6
D
C1
1D
R
13
Q
D
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
typical load, count, and inhibit sequences
SN74ALS568A
OE
ACLR
SCLR
LOAD
Don’t Care
ENP
Don’t Care
ENT
Don’t Care
U/D
CLK
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
A
B
C
D
Q
Q
Q
Q
Hi Z
Hi Z
Hi Z
Hi Z
A
B
C
D
RCO
CCO
1
2
0
7
8
9
0
1
2
3
4
3
2
1
0
9
8
Count
Up
Inhibit
Counting
Count Up
Count Down
Async
Clear
Sync Sync
Clear Load
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
typical load, count, and inhibit sequences (continued)
′ALS569A
OE
ACLR
SCLR
LOAD
ENP
Don’t Care
Don’t Care
ENT
Don’t Care
U/D
CLK
A
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
B
C
D
Q
A
Hi Z
Hi Z
Hi Z
Hi Z
Q
B
Q
C
Q
D
RCO
CCO
1
2
0
13 14 15
0
1
2
3
4
3
2
1
0
15 14
Count
Up
Inhibit
Counting
Count Up
Count Down
Async
Clear
Sync Sync
Clear Load
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, T : SN54ALS569A . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74ALS568A, SN74ALS569A . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN74ALS568A
SN74ALS569A
SN54ALS569A
MIN NOM MAX
UNIT
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
0.7
–1
0.8
–2.6
–0.4
24
Q outputs
I
I
f
High-level output current
Low-level output current
Clock frequency
mA
mA
OH
CCO and RCO
Q outputs
–0.4
12
OL
CCO and RCO
SN74ALS568A
′ALS569A
4
8
0
0
20
MHz
clock
0
22
30
ACLR or LOAD low
20
15
25
25
16.5
16.5
20
30
20
15
30
15
30
30
10
0
CLK high
CLK low
CLK high
CLK low
SN74ALS568A
t
w
Pulse duration
ns
20
23
25
35
25
20
35
20
35
35
10
0
′ALS569A
Data at A, B, C, D
ENP, ENT
High
Low
Low
SCLR
LOAD
t
t
High (inactive)
Low
ns
Setup time before CLK↑
su
High (inactive)
U/D
ACLR inactive
Hold time after CLK↑ for any input
ns
h
T
A
Operating free-air temperature
–55
125
0
70
°C
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74ALS568A
SN54ALS569A
SN74ALS569A
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.5
–1.5
V
IK
CC
I
All outputs
Q outputs
= 4.5 V to 5.5 V,
I
I
I
I
I
I
I
= –0.4 mA
= –1 mA
= –2.6 mA
= 12 mA
= 24 mA
= 4 mA
V
–2
V
CC
–2
CC
OH
OH
OH
OL
OL
OL
OL
CC
2.4
3.3
0.25
0.25
V
OH
V
CC
V
CC
V
CC
= 4.5 V
= 4.5 V
= 4.5 V
2.4
3.2
0.25
0.35
0.25
0.35
0.4
0.4
0.4
0.5
0.4
0.5
20
Q outputs
V
OL
V
CCO and RCO
= 8 mA
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
= 2.7 V
20
–20
0.1
µA
µA
OZH
OZL
I
O
O
V
= 0.4 V
–20
0.1
20
V = 7 V
I
mA
µA
V = 2.7 V
I
20
IH
V = 0.4 V
I
–0.2
–70
–112
26
–0.2
–70
–112
26
mA
IL
–15
–20
–15
–30
CCO and RCO
Q outputs
‡
V
= 5.5 V,
V
O
= 2.25 V
mA
I
O
CC
CC
Outputs high
Outputs low
16
20
20
16
20
20
I
V
= 5.5 V
32
32
mA
CC
Outputs disabled
32
32
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
switching characteristics (see Figure 1)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
R1 = 500 Ω,
R2 = 500 Ω,
T
A
FROM
(INPUT)
TO
(OUTPUT)
†
= MIN to MAX
PARAMETER
UNIT
SN74ALS568A
SN74ALS569A
SN54ALS569A
MIN
MAX
MIN
20
30
4
MAX
SN74ALS568A
f
MHz
ns
max
′ALS569A
22
4
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
21
19
37
28
17
30
31
33
21
20
18
32
18
18
25
23
29
12
29
13
16
28
19
13
25
23
19
15
13
13
23
12
14
20
18
24
10
13
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PHL
PZH
PZL
PHZ
PLZ
CLK
CLK
CLK
U/D
Any Q
RCO
CCO
RCO
RCO
CCO
7
7
12
10
5
12
10
5
ns
ns
6
6
9
9
ns
9
9
6
6
ns
ENT
ENT
4
4
5
5
ns
9
9
4
4
ns
ns
ns
ENP
ACLR
OE
CCO
Any Q
Any Q
5
5
9
9
6
6
6
6
1
1
ns
OE
Any Q
3
3
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
h
t
w
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
83025022A
8302502RA
ACTIVE
ACTIVE
FK
J
20
20
20
20
20
20
1
1
1
1
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Call TI
8302502SA
ACTIVE
W
J
SN54ALS569AJ
SN74ALS568AN
SN74ALS569ADW
ACTIVE
CDIP
PDIP
SOIC
A42 SNPB
Call TI
OBSOLETE
ACTIVE
N
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS569ADWE4
SN74ALS569ADWG4
SN74ALS569ADWR
SN74ALS569ADWRE4
SN74ALS569ADWRG4
SN74ALS569AN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
DW
DW
DW
DW
DW
N
20
20
20
20
20
20
20
20
20
20
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74ALS569ANE4
SN74ALS569ANSR
SN74ALS569ANSRE4
SN74ALS569ANSRG4
N
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NS
NS
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54ALS569AFK
SNJ54ALS569AJ
SNJ54ALS569AW
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
20
20
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2008
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
(mm)
SN74ALS569ADWR
DW
20
SITE 41
330
24
10.8
13.0
2.7
12
24
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2008
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74ALS569ADWR
DW
20
SITE 41
346.0
346.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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