SN74ALVC00PWRE4 [TI]
QUADRUPLE 2-INPUT POSITIVE-NAND GATE; 四路2输入正与非门型号: | SN74ALVC00PWRE4 |
厂家: | TEXAS INSTRUMENTS |
描述: | QUADRUPLE 2-INPUT POSITIVE-NAND GATE |
文件: | 总16页 (文件大小:726K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN74ALVC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
www.ti.com
SCES115G–JULY 1997–REVISED AUGUST 2004
FEATURES
•
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
•
•
•
•
Operates From 1.65 V to 3.6 V
Max tpd of 3 ns at 3.3 V
±24-mA Output Drive at 3.3 V
– 1000-V Charged-Device Model (C101)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D, DGV, NS, OR PW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
V
CC
4B
4A
4Y
3B
3A
3Y
1
14
1Y
2A
2B
2Y
1B
1Y
2A
2B
2Y
13 4B
2
3
4
5
6
12
11
10
9
4A
4Y
3B
3A
8
GND
7
8
DESCRIPTION/ORDERING INFORMATION
This quadruple 2-input positive-NAND gate is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVC00 performs the Boolean function Y = A · B or Y = A + B in positive logic.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74ALVC00RGYR
SN74ALVC00D
TOP-SIDE MARKING
QFN - RGY
SOIC - D
Tape and reel
VA00
Tube
ALVC00
Tape and reel
Tape and reel
Tape and reel
Tape and reel
SN74ALVC00DR
-40°C to 85°C
SOP - NS
SN74ALVC00NSR
ALVC00
VA00
TSSOP - PW
TVSOP - DGV
SN74ALVC00PWR
SN74ALVC00DGVR
VA00
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
H
L
B
H
X
L
L
H
H
X
LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)
A
Y
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1997–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74ALVC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
www.ti.com
SCES115G–JULY 1997–REVISED AUGUST 2004
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
-0.5
-0.5
-0.5
MAX
4.6
UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Output voltage range(2)(3)
V
4.6
VCC + 0.5
-50
V
VO
IIK
V
Input clamp current
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
-50
Continuous output current
Continuous current through VCC or GND
±50
±100
86
D package(4)
DGV package(4)
NS package(4)
PW package(4)
RGY package(5)
127
θJA
Package thermal impedance
76
°C/W
113
47
Tstg
Storage temperature range
-65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
RECOMMENDED OPERATING CONDITIONS(1)
MIN
MAX UNIT
VCC
Supply voltage
1.65
3.6
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
0.35 × VCC
VIL
Low-level input voltage
0.7
0.8
3.6
VCC
-4
V
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
-12
-12
-24
4
IOH
High-level output current
Low-level output current
mA
mA
VCC= 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
12
12
24
5
IOL
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
TA
-40
85
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
SN74ALVC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
www.ti.com
SCES115G–JULY 1997–REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V VCC - 0.2
MIN TYP(1) MAX UNIT
IOH = -100 µA
IOH = -4 mA
IOH = -6 mA
1.65 V
2.3 V
1.2
2
VOH
2.3 V
1.7
2.2
2.4
2
V
IOH = -12 mA
2.7 V
3 V
IOH = -24 mA
IOL = 100 µA
IOL = 4 mA
IOL = 6 mA
3 V
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
VOL
V
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
3 V
0.55
±5
II
VI = VCC or GND
3.6 V
µA
µA
µA
pF
ICC
∆ICC
Ci
VI = VCC or GND, IO= 0
3.6 V
10
One input at VCC - 0.6 V, Other inputs at VCC or GND
VI = VCC or GND
3 V to 3.6 V
3.3 V
750
4.5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
4.4
MIN
MAX
MIN
MAX
3.2
MIN
MAX
tpd
A or B
Y
1
1
2.8
1
3
ns
OPERATING CHARACTERISTICS
TA = 25°C
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
PARAMETER
TEST CONDITIONS
UNIT
Cpd
Power dissipation capacitance per gate
CL = 0 pF, f = 10 MHz
20
21
23
pF
3
SN74ALVC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
www.ti.com
SCES115G–JULY 1997–REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
S1
GND
t
Open
V
LOAD
GND
pd
/t
/t
C
t
t
L
PLZ PZL
R
L
(see Note A)
PHZ PZH
LOAD CIRCUIT
INPUT
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
V
V
2.7 V
2.7 V
V
/2
/2
2 × V
2 × V
6 V
6 V
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
30 pF
30 pF
50 pF
50 pF
CC
CC
CC
V
CC
CC
CC
1.5 V
1.5 V
3.3 V ± 0.3 V
0.3 V
t
w
V
I
V
I
V
M
V
M
Input
Timing
Input
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
I
Output
Control
(low-level
enabling)
Data
Input
V
I
V
V
M
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at V
LOAD
(see Note B)
V
V
/2
LOAD
V
I
V
M
Input
V
M
V
M
V + V
∆
OL
0 V
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− V
∆
V
M
Output
V
M
V
M
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
4
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Copyright © 2007, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
PACKAGING INFORMATION
Orderable Device
SN74ALVC00D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALVC00DE4
SOIC
SOIC
TVSOP
TVSOP
TVSOP
SOIC
SOIC
SOIC
SO
D
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALVC00DG4
SN74ALVC00DGVR
SN74ALVC00DGVRE4
SN74ALVC00DGVRG4
SN74ALVC00DR
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGV
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALVC00DRE4
SN74ALVC00DRG4
SN74ALVC00NSR
SN74ALVC00NSRE4
SN74ALVC00NSRG4
SN74ALVC00PWR
SN74ALVC00PWRE4
SN74ALVC00PWRG4
SN74ALVC00RGYR
SN74ALVC00RGYRG4
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
NS
NS
NS
PW
PW
PW
RGY
RGY
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
QFN
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
180
(mm)
12
SN74ALVC00DGVR
SN74ALVC00DR
DGV
D
14
14
14
14
14
SITE 41
SITE 41
SITE 41
SITE 41
SITE 41
6.8
6.5
4.0
9.0
1.6
2.1
8
8
16
16
16
12
12
Q1
Q1
Q1
Q1
Q1
16
SN74ALVC00NSR
SN74ALVC00PWR
SN74ALVC00RGYR
NS
16
8.2
10.5
5.6
2.5
12
8
PW
RGY
12
7.0
1.6
12
3.85
3.85
1.35
8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74ALVC00DGVR
SN74ALVC00DR
DGV
D
14
14
14
14
14
SITE 41
SITE 41
SITE 41
SITE 41
SITE 41
346.0
346.0
346.0
346.0
190.0
346.0
346.0
346.0
346.0
212.7
29.0
33.0
33.0
29.0
31.75
SN74ALVC00NSR
SN74ALVC00PWR
SN74ALVC00RGYR
NS
PW
RGY
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
相关型号:
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