SN74ALVC162835 [TI]
18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS; 18位通用总线驱动器，具有三态输出
| 型号： | SN74ALVC162835 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS |
| 文件： | 总11页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALVC162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
NC
Y1
GND
Y2
Y3
GND
NC
A1
GND
A2
A3
2
Ideal for Use in PC100 Register DIMM
Revision 1.1
3
4
Output Port Has Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
5
6
7
V
V
CC
Y4
CC
8
A4
A5
A6
GND
A7
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
9
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Latch-Up Performance Exceeds 250 mA Per
JESD 17
A8
A9
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
A10
A11
A12
GND
A13
A14
A15
description
This 18-bit universal bus driver is designed for
1.65-V to 3.6-V V operation.
CC
V
V
CC
CC
Data flow from A to Y is controlled by the
output-enable (OE) input. The device operates in
the transparent mode when the latch-enable (LE)
input is high. When LE is low, the A data is latched
if the clock (CLK) input is held at a high or low logic
level. If LE is low, the A data is stored in the
latch/flip-flop on the low-to-high transition of CLK.
When OE is high, the outputs are in the
high-impedance state.
Y16
Y17
GND
Y18
OE
A16
A17
GND
A18
CLK
GND
LE
NC – No internal connection
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The output port includes equivalent 26-Ω series resistors to reduce overshoot and undershoot.
The SN74ALVC162835 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE
H
L
LE
X
H
H
L
CLK
A
X
L
X
Z
L
X
L
X
H
L
H
L
L
↑
↑
L
L
H
X
H
†
Y
0
L
L
L or H
†
Output level before the indicated steady-state
input conditions were established
‡
logic symbol
27
30
EN1
2C3
OE
CLK
28
LE
C3
G2
3
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
1
Y1
Y2
1
3D
A1
5
A2
6
Y3
A3
8
Y4
A4
9
Y5
A5
10
12
13
14
15
16
17
19
20
21
23
24
26
Y6
A6
Y7
A7
Y8
A8
Y9
A9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
A10
A11
A12
A13
A14
A15
A16
A17
A18
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999
logic diagram (positive logic)
27
OE
30
CLK
28
LE
54
A1
1D
C1
3
Y1
CLK
To 17 Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999
recommended operating conditions (see Note 4)
MIN
1.65
MAX
UNIT
V
Supply voltage
3.6
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
0.65 × V
1.7
CC
V
High-level input voltage
V
V
2
0.35 × V
0.7
CC
V
IL
Low-level input voltage
0.8
V
V
Input voltage
0
0
V
V
V
V
I
CC
Output voltage
O
CC
–2
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
–6
–8
I
High-level output current
Low-level output current
mA
mA
OH
OL
–12
2
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
6
I
8
12
10
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
A
–40
°C
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
–0.2
MAX
UNIT
V
CC
I
I
I
= –100 µA
= –2 mA
= –4 mA
1.65 V to 3.6 V
1.65 V
2.3 V
V
OH
OH
OH
CC
1.2
1.9
1.7
2.4
2
V
OH
2.3 V
V
I
= –6 mA
OH
3 V
I
I
I
I
I
= –8 mA
= –12 mA
= 100 µA
= 2 mA
2.7 V
OH
OH
OL
OL
OL
3 V
2
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
= 4 mA
V
OL
2.3 V
0.55
0.55
0.6
V
I
= 6 mA
OL
3 V
I
I
= 8 mA
2.7 V
OL
= 12 mA
3 V
0.8
OL
I
I
I
V = V
or GND
3.6 V
±5
µA
µA
µA
µA
I
I
CC
V
O
= V
or GND
3.6 V
±10
40
OZ
CC
CC
V = V
I
or GND,
– 0.6 V,
I
= 0
3.6 V
CC
O
∆I
CC
One input at V
Other inputs at V
CC
or GND
3 V to 3.6 V
750
CC
Control inputs
Data inputs
Outputs
3.5
5
C
V = V or GND
CC
3.3 V
3.3 V
pF
pF
i
I
C
V
O
= V
or GND
7
o
CC
†
All typical values are at V
= 3.3 V, T = 25°C.
CC
A
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
V = 2.5 V
CC
± 0.2 V
V = 3.3 V
CC
± 0.3 V
V
CC
= 1.8 V
V
CC
= 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
‡
f
t
Clock frequency
Pulse duration
150
150
150
MHz
ns
clock
‡
‡
‡
‡
‡
‡
LE high
3.3
3.3
2.2
1.9
1.3
0.6
3.3
3.3
2.1
1.6
1.1
0.6
3.3
3.3
1.7
1.5
1
w
CLK high or low
Data before CLK↑
t
su
Setup time
Hold time
CLK high
CLK low
ns
ns
Data before LE↓
Data after CLK↑
Data after LE↓
0.7
t
h
CLK
high or low
‡
1.4
1.7
1.4
‡
This information was not available at the time of publication.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
V
= 2.5 V
V
= 3.3 V
CC
± 0.2 V
CC
± 0.3 V
V
= 1.8 V
TYP
V
= 2.7 V
MAX
FROM
(INPUT)
TO
(OUTPUT)
CC
CC
PARAMETER
UNIT
MIN
MIN
150
1
MAX
MIN
MIN
150
1
MAX
†
f
150
MHz
max
pd
†
†
†
†
†
A
5
5.9
6.3
6.3
4.9
5
5.8
6.1
6.5
4.9
4.2
5.1
5.4
5.5
4.5
t
LE
Y
1.3
1.4
1.4
1
1.3
1.4
1.1
1.3
ns
CLK
OE
OE
t
t
Y
Y
ns
ns
en
dis
†
This information was not available at the time of publication.
switching characteristics from 0°C to 85°C, C = 0 pF
L
V
= 3.3 V
± 0.15 V
CC
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
UNIT
MIN
MAX
A
Y
Y
0.9
2
ns
ns
‡
t
pd
CLK
1.4
2.9
‡
Texas Instruments SPICE simulation data
switching characteristics from 0°C to 65°C, C = 50 pF
L
V
= 3.3 V
CC
± 0.15 V
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
UNIT
MIN
MAX
A
Y
Y
1
4
ns
ns
t
pd
CLK
1.9
5
operating characteristics, T = 25°C
A
V
= 1.8 V
CC
TYP
V
= 2.5 V
CC
TYP
V = 3.3 V
CC
PARAMETER
TEST CONDITIONS
UNIT
TYP
†
†
Outputs enabled
Outputs disabled
35.5
12.5
40
14
Power dissipation
capacitance
C
C
= 0,
L
f = 10 MHz
pF
pd
†
This information was not available at the time of publication.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
= 1.8 V
V
CC
2 × V
CC
Open
S1
1 kΩ
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
1 kΩ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
= 2.7 V AND 3.3 V ± 0.3 V
V
CC
6 V
Open
S1
TEST
S1
500 Ω
From Output
Under Test
t
pd
Open
6 V
GND
t
/t
PLZ PZL
/t
C
= 50 pF
t
GND
L
PHZ PZH
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
2.7 V
0 V
1.5 V
1.5 V
Input
2.7 V
0 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
2.7 V
0 V
Data
Input
1.5 V
1.5 V
2.7 V
0 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
3 V
2.7 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
+ 0.3 V
OL
V
(see Note B)
OL
OH
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
V
OH
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 3. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999
TYPICAL CHARACTERISTICS
0
ALVC162835 Pullup
–0.01
x
PC100 Requirements
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
–0.09
–0.1
0
0.5
1.0
1.5
2.0
2.5
3.0
V
OH
– Output Voltage – V
Figure 4. IV Characteristics – Pullup
0.12
0.10
0.08
0.06
0.04
0.02
0.00
ALVC162835 Pulldown
x
PC100 Requirements
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
V
OL
– Output Voltage – V
Figure 5. IV Characteristics – Pulldown
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明