SN74ALVC164245_08 [TI]
16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS; 16位2.5 V至3.3 V / 3.3 V至具有三态输出的5V电平转换收发器
| 型号： | SN74ALVC164245_08 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS |
| 文件： | 总22页 (文件大小：656K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALVC164245
16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS416P–MARCH 1994–REVISED NOVEMBER 2005
FEATURES
DGG OR DL PACKAGE
•
Member of the Texas Instruments Widebus™
(TOP VIEW)
Family
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
•
•
•
Max tpd of 5.8 ns at 3.3 V
±24-mA Output Drive at 3.3 V
2
3
Control Inputs VIH/VIL Levels Are Referenced
to VCCA Voltage
4
5
•
Latch-Up Performance Exceeds 250 mA Per
JESD 17
6
7
(3.3 V, 5 V) V
V
CCA
(2.5 V, 3.3 V)
CCB
8
1B5
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
NOTE: New and improved versions of the SN74ALVC164245
are available. The new part numbers are SN74LVC16T245 and
SN74LVCH16T245 and should be considered for new designs.
9
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DESCRIPTION/ORDERING INFORMATION
This 16-bit (dual-octal) noninverting bus transceiver
contains two separate supply rails. B port has VCCB
which is set to operate at 3.3 V and 5 V. A port has
VCCA, which is set to operate at 2.5 V and 3.3 V. This
allows for translation from a 2.5-V to a 3.3-V
environment, and vice versa, or from a 3.3-V to a 5-V
environment, and vice versa.
,
(3.3 V, 5 V) V
V
CCA
(2.5 V, 3.3 V)
CCB
2B5
2A5
2A6
GND
2A7
2A8
2OE
2B6
GND
2B7
2B8
2DIR
The SN74ALVC164245 is designed for asynchronous
communication between data buses. The control
circuitry (1DIR, 2DIR, 1OE, and 2OE) is powered by
VCCA
.
To ensure the high-impedance state during power up
or power down, the output-enable (OE) input should
be tied to VCC through a pullup resistor; the minimum
value of the resistor is determined by the
current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
74ALVC164245GRDR
74ALVC164245ZRDR
TOP-SIDE MARKING
FBGA – GRD
Tape and reel
Tube of 25
VC4245
FBGA – ZRD (Pb-free)
SN74ALVC164245DL
SSOP – DL
SN74ALVC164245DLR
74ALVC164245DLRG4
SN74ALVC164245DGGR
74ALVC164245DGGRG4
SN74ALVC164245DGGT
74ALVC164245DGGTE4
SN74ALVC164245KR
ALVC164245
Reel of 1000
–40°C to 85°C
Reel of 2000
Reel of 250
Reel of 1000
TSSOP – DGG
ALVC164245
VC4245
VFBGA – GQL
VFBGA – ZQL (Pb-free)
74ALVC164245ZQLR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1994–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74ALVC164245
16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS416P–MARCH 1994–REVISED NOVEMBER 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port
outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data
from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the
A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic
HIGH or LOW level applied to prevent excess ICC and ICCZ
.
TERMINAL ASSIGNMENTS(1)
(56-Ball GQL/ZQL Package)
GQL OR ZQL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
1
2 3 4 5 6
A
B
C
D
E
F
1DIR
1B2
1B4
1B6
1B8
2B1
2B3
2B5
2B7
2DIR
NC
NC
NC
NC
1OE
1A2
1A4
1A6
1A8
2A1
2A3
2A5
2A7
2OE
A
B
C
D
E
F
G
H
J
1B1
1B3
1B5
1B7
2B2
2B4
2B6
2B8
NC
GND
VCCB
GND
GND
VCCA
GND
1A1
1A3
1A5
1A7
2A2
2A4
2A6
2A8
NC
G
H
J
GND
VCCB
GND
NC
GND
VCCA
GND
NC
K
K
abc
abc
(1) NC – No internal connection
GRD OR ZRD PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS(1)
(54-Ball GRD/ZRD Package)
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1B1
1B3
1B5
1B7
2B1
2B3
2B5
2B7
2B8
NC
1DIR
NC
1OE
NC
NC
1A1
1A3
1A5
1A7
2A1
2A3
2A5
2A7
2A8
A
B
C
D
1B2
1B4
1B6
1B8
2B2
2B4
2B6
NC
1A2
1A4
1A6
1A8
2A2
2A4
2A6
NC
VCCB
GND
GND
GND
VCCB
NC
VCCA
GND
GND
GND
VCCA
NC
E
F
G
H
J
G
H
J
2DIR
2OE
(1) NC – No internal connection
xxxxx
xxxxx
xxxxx
xxxxx
FUNCTION TABLE(1)
(EACH 8-BIT SECTION)
CONTROL INPUTS
OUTPUT CIRCUITS
OPERATION
OE
L
DIR
L
A PORT
Enabled
Hi-Z
B PORT
Hi-Z
B data to A bus
A data to B bus
Isolation
L
H
Enabled
Hi-Z
H
X
Hi-Z
(1) Input circuits of the data I/Os always are active.
2
SN74ALVC164245
16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS416P–MARCH 1994–REVISED NOVEMBER 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
24
1
2DIR
1DIR
48
25
13
1OE
1B1
2OE
2B1
36
47
1A1
2A1
2
To Seven Other Channels
To Seven Other Channels
Absolute Maximum Ratings(1)
over operating free-air temperature range for VCCB at 5 V and VCCA at 3.3 V (unless otherwise noted)
MIN
MAX
4.6
6
UNIT
VCCA
–0.5
–0.5
–0.5
VCC
Supply voltage range
Input voltage range
V
VCCB
Except I/O ports(2)
I/O port A(3)
I/O port B(2)
VI < 0
6
VI
–0.5 VCCA + 0.5
V
–0.5 VCCB + 0.5
IIK
IOK
IO
Input clamp current
–50
–50
±50
±100
70
mA
mA
mA
mA
Output clamp current
VO < 0
Continuous output current
Continuous current through each VCC or GND
DGG package
DL package
63
θJA
Package thermal impedance(4)
°C/W
°C
GQL/ZQL package
GRD/ZRD package
42
36
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) This value is limited to 6 V maximum.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
3
SN74ALVC164245
16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS416P–MARCH 1994–REVISED NOVEMBER 2005
Recommended Operating Conditions(1)
for VCCB at 3.3 V and 5 V
MIN
3
MAX
5.5
UNIT
VCCB
VIH
Supply voltage
V
High-level input voltage
2
V
VCCB = 3 V to 3.6 V
VCCB = 4.5 V to 5.5 V
0.7
0.8
VIL
Low-level input voltage
V
VIB
Input voltage
0
0
VCCB
VCCB
–24
24
V
V
VOB
IOH
IOL
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
mA
mA
ns/V
°C
∆t/∆v
TA
10
–40
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Recommended Operating Conditions(1)
for VCCA at 2.5 V and 3.3 V
MIN
2.3
1.7
2
MAX
UNIT
VCCA
VIH
Supply voltage
3.6
V
VCCA = 2.3 V to 2.7 V
VCCA = 3 V to 3.6 V
VCCA = 2.3 V to 2.7 V
VCCA = 3 V to 3.6 V
High-level input voltage
V
V
0.7
0.8
VIL
Low-level input voltage
VIA
Input voltage
0
0
VCCA
VCCA
–18
–24
18
V
V
VOA
Output voltage
VCCA = 2.3 V
VCCA = 3 V
VCCA = 2.3 V
VCCA = 3 V
IOH
High-level output current
Low-level output current
mA
mA
IOL
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
TA
–40
85
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
SN74ALVC164245
16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS416P–MARCH 1994–REVISED NOVEMBER 2005
Electrical Characteristics
over recommended operating free-air temperature range for VCCA = 2.7 V to 3.6 V and VCCB = 4.5 V to 5.5 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VCCA
2.7 V to 3.6 V
2.7 V
VCCB
MIN
TYP(1) MAX
UNIT
VCC – 0.2
2.2
2.4
2
B to A
IOH = –12 mA
IOH = –24 mA
IOH = –100 µA
3 V
3 V
VOH
V
4.5 V
5.5 V
4.5 V
5.5 V
4.3
5.3
3.7
4.7
A to B
IOH = –24 mA
IOL = 100 µA
IOL = 12 mA
IOL = 24 mA
IOL = 100 µA
IOL = 24 mA
2.7 V to 3.6 V
2.7 V
0.2
0.4
B to A
A to B
VOL
3 V
0.55
0.2
V
4.5 V to 5.5 V
4.5 V to 5.5 V
5.5 V
0.55
±5
II
IOZ
ICC
Control inputs VI = VCCA/VCCB or GND
3.6 V
3.6 V
3.6 V
µA
µA
µA
(2)
A or B port
VO = VCCA/VCCB or GND
5.5 V
±10
40
VI = VCCA/VCCB or GND, IO = 0
5.5 V
One input at VCCA/VCCB – 0.6 V,
Other inputs at VCCA/VCCB or GND
(3)
∆ICC
3 V to 3.6 V
4.5 V to 5.5 V
750
µA
Ci
Control inputs VI = VCCA/VCCB or GND
A or B port VO = VCCA/VCCB or GND
3.3 V
3.3 V
5 V
6.5
8.5
pF
pF
Cio
3.3 V
(1) Typical values are measured at VCCA = 3.3 V and VCCB = 5 V, TA = 25°C.
(2) For I/O ports, the parameter IOZ includes the input leakage current.
(3) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than at 0 or the associated
VCC
.
Electrical Characteristics
over recommended operating free-air temperature range for VCCA = 2.3 V to 2.7 V and VCCB = 3 V to 3.6 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VCCA
VCCB
MIN
VCCA – 0.2
1.7
MAX
UNIT
2.3 V to 2.7 V
2.3 V
3 V to 3.6 V
3 V to 3.6 V
3 V to 3.6 V
3 V to 3.6 V
3 V
B to A
IOH = –8 mA
IOH = –12 mA
IOH = –100 µA
IOH = –18 mA
IOL = 100 µA
IOL = 12 mA
IOL = 100 µA
IOL = 18 mA
VOH
2.7 V
1.8
V
2.3 V to 2.7 V
2.3 V to 2.7 V
2.3 V to 2.7 V
2.3 V
VCCB – 0.2
2.2
A to B
B to A
A to B
3 V to 3.6 V
3 V to 3.6 V
3 V to 3.6 V
3 V
0.2
0.6
0.2
0.55
±5
VOL
V
2.3 V to 2.7 V
2.3 V
II
IOZ
ICC
Control inputs VI = VCCA/VCCB or GND
2.3 V to 2.7 V
2.3 V to 2.7 V
2.3 V to 2.7 V
3 V to 3.6 V
3 V to 3.6 V
3 V to 3.6 V
µA
µA
µA
(1)
A or B port
VO = VCCA/VCCB or GND
±10
20
VI = VCCA/VCCB or GND, IO = 0
One input at VCCA/VCCB – 0.6 V,
Other inputs at VCCA/VCCB or GND
(2)
∆ICC
2.3 V to 2.7 V
3 V to 3.6 V
750
µA
(1) For I/O ports, the parameter IOZ includes the input leakage current.
(2) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than at 0 or the associated
VCC
.
5
SN74ALVC164245
16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS416P–MARCH 1994–REVISED NOVEMBER 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 4)
VCCB = 3.3 V
VCCB = 5 V ± 0.5 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
VCCA = 2.5 V
VCCA = 3.3 V
UNIT
VCCA = 2.7 V
MIN MAX
± 0.2 V
± 0.3 V
MIN
MAX
MIN
1
MAX
5.8
5.8
8.9
9.5
9.1
8.6
A
B
A
B
B
A
A
7.6
7.6
5.9
6.7
9.3
9.2
10.2
9
tpd
ns
B
1.2
1
ten
tdis
ten
tdis
OE
OE
OE
OE
11.5
10.5
12.3
9.3
ns
ns
ns
ns
2.1
2
2.9
Operating Characteristics
TA = 25°C
VCCB = 3.3 V
VCCB = 5 V
PARAMETER
TEST CONDITIONS
VCCA = 2.5 V
VCCA = 3.3 V
UNIT
TYP
55
TYP
56
6
Outputs enabled (B)
Outputs disabled (B)
Outputs enabled (A)
Outputs disabled (A)
CL = 50 pF, f = 10 MHz
CL = 50 pF, f = 10 MHz
27
Cpd
Power dissipation capacitance
pF
118
58
56
6
6
SN74ALVC164245
16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS416P–MARCH 1994–REVISED NOVEMBER 2005
(1)
POWER-UP CONSIDERATIONS
TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up
sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other
anomalies caused by improperly biased device pins. Take these precautions to guard against such power-up
problems:
1. Connect ground before any supply voltage is applied.
2. Power up the control side of the device (VCCA for all four of these devices).
3. Tie OE to VCCA with a pullup resistor so that it ramps with VCCA
.
4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus),
ramp it with VCCA. Otherwise, keep DIR low.
(1) Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021.
7
SN74ALVC164245
16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS416P–MARCH 1994–REVISED NOVEMBER 2005
PARAMETER MEASUREMENT INFORMATION
VCCA = 2.5 V ± 0.2 V to VCCB = 3.3 V ± 0.3 V
V
CCB
= 6 V
TEST
S1
S1
500 Ω
Open
GND
t
Open
pd
From Output
Under Test
t
t
/t
/t
V
= 6 V
PLZ PZL
CCB
GND
PHZ PZH
C = 30 pF
(see Note A)
L
500 Ω
LOAD CIRCUIT
V
CCA
Output
Control
(low-level
enabling)
V /2
CCA
V /2
CCA
0 V
t
t
PLZ
PZL
V
V
CCB
Output
Waveform 1
S1 at 6 V
V
CCA
1.5 V
1.5 V
Input
V /2
CCA
V /2
CCA
V
+ 0.3 V
OL
OLB
0 V
(see Note B)
t
t
t
t
PLH
PHL
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OHB
V
OHB
V
OH
− 0.3 V
Output
1.5 V
1.5 V
(see Note B)
0 V
V
OLB
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, Z = 50 Ω, t ≤2 ns, t ≤2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
8
SN74ALVC164245
16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS416P–MARCH 1994–REVISED NOVEMBER 2005
PARAMETER MEASUREMENT INFORMATION
VCCB = 3.3 V ± 0.3 V to VCCA = 2.5 V ± 0.2 V
2 × V
CCA
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
t
pd
Open
C = 30 pF
(see Note A)
L
t
/t
/t
2 × V
CCA
GND
PLZ PZL
500 Ω
t
PHZ PZH
LOAD CIRCUIT
Output
Control
(low-level
enabling)
2.7 V
0 V
1.5 V
1.5 V
t
t
PLZ
PZL
Output
Waveform 1
V
CCA
2.7 V
0 V
V
/2
CCA
Input
1.5 V
1.5 V
V
V
+ 0.15 V
S1 at 2 × V
OL
CCA
V
OLA
(see Note B)
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OHA
V
V
OHA
− 0.15 V
OH
V
/2
CCA
Output
V /2
CCA
V /2
CCA
0 V
OLA
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, Z = 50 Ω, t ≤2 ns, t ≤2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 2. Load Circuit and Voltage Waveforms
9
SN74ALVC164245
16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS416P–MARCH 1994–REVISED NOVEMBER 2005
PARAMETER MEASUREMENT INFORMATION
VCCA = 3.3 V ± 0.3 V to VCCB = 5 V ± 0.5 V
2
V
CCB
TEST
S1
S1
Open
GND
500 Ω
t
Open
pd
/t
/t
From Output
Under Test
t
t
2 V
PLZ PZL
CCB
GND
PHZ PZH
C = 50 pF
L
500 Ω
(see Note A)
2.7 V
0 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
LOAD CIRCUIT
t
t
t
PLZ
PZL
Output
Waveform 1
≈V
CCB
2.7 V
0 V
50% V
CCB
Input
S1 at 2 V
1.5 V
1.5 V
20% V
CCB
(see Note B)
CCB
V
OL
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
80% V
OH
CCB
50% V
CCB
Output
50% V
50% V
CCB
CCB
0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 3. Load Circuit and Voltage Waveforms
10
SN74ALVC164245
16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS416P–MARCH 1994–REVISED NOVEMBER 2005
PARAMETER MEASUREMENT INFORMATION
VCCB = 5 V ± 0.5 V to VCCA = 2.7 V and 3.3 V ± 0.3 V
V
CCA
= 6 V
TEST
S1
S1
Open
GND
500 Ω
t
Open
pd
/t
From Output
Under Test
t
V
= 6 V
PLZ PZL
CCA
t
/t
GND
PHZ PZH
C = 50 pF
(see Note A)
L
500 Ω
3 V
0 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
LOAD CIRCUIT
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
≈3 V
3 V
1.5 V
Input
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
OLA
(see Note B)
0 V
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OHA
V
OHA
− 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
0 V
V
OLA
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 4. Load Circuit and Voltage Waveforms
11
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
74ALVC164245DGGRE4
74ALVC164245DGGRG4
74ALVC164245DGGTE4
74ALVC164245DGGTG4
74ALVC164245DLG4
74ALVC164245DLRG4
74ALVC164245GRDR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
48
48
48
48
48
54
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
SSOP
DGG
DGG
DGG
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
GRD
1000
TBD
SNPB
Level-1-240C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
74ALVC164245ZQLR
74ALVC164245ZRDR
ACTIVE
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQL
ZRD
56
54
1000 Green (RoHS &
no Sb/Br)
SNAGCU
SNAGCU
BGA MI
CROSTA
R JUNI
OR
1000 Green (RoHS &
no Sb/Br)
SN74ALVC164245DGGR
SN74ALVC164245DGGT
SN74ALVC164245DL
SN74ALVC164245DLR
SN74ALVC164245KR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
SSOP
DGG
DGG
DL
48
48
48
48
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
GQL
1000
TBD
SNPB
Level-1-240C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74ALVC164245 :
Enhanced Product: SN74ALVC164245-EP
•
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
74ALVC164245GRDR BGA MI
GRD
ZQL
ZRD
54
56
54
1000
330.0
330.0
330.0
16.4
16.4
16.4
5.8
8.3
1.55
8.0
8.0
8.0
16.0
16.0
16.0
Q1
Q1
Q1
CROSTA
R JUNI
OR
74ALVC164245ZQLR
74ALVC164245ZRDR
BGA MI
CROSTA
R JUNI
OR
1000
1000
4.8
5.8
7.3
8.3
1.45
1.55
BGA MI
CROSTA
R JUNI
OR
SN74ALVC164245DGGR TSSOP
DGG
DL
48
48
56
2000
1000
1000
330.0
330.0
330.0
24.4
32.4
16.4
8.6
11.35
4.8
15.8
16.2
7.3
1.8
3.1
12.0
16.0
8.0
24.0
32.0
16.0
Q1
Q1
Q1
SN74ALVC164245DLR
SN74ALVC164245KR
SSOP
BGA MI
CROSTA
R JUNI
OR
GQL
1.45
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
74ALVC164245GRDR BGA MICROSTAR
JUNIOR
GRD
ZQL
ZRD
54
56
54
1000
346.0
346.0
346.0
346.0
346.0
346.0
33.0
33.0
33.0
74ALVC164245ZQLR
BGA MICROSTAR
JUNIOR
1000
1000
74ALVC164245ZRDR
BGA MICROSTAR
JUNIOR
SN74ALVC164245DGGR
SN74ALVC164245DLR
SN74ALVC164245KR
TSSOP
SSOP
DGG
DL
48
48
56
2000
1000
1000
346.0
346.0
346.0
346.0
346.0
346.0
41.0
49.0
33.0
BGA MICROSTAR
JUNIOR
GQL
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
SN74ALVC16501DGG
ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, PLASTIC, TSSOP-56
TI
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