SN74ALVC16901DGGR [TI]
18-Bit Universal Bus Transceiver with Parity Generators/Checkers 64-TSSOP -40 to 85;
| 型号： | SN74ALVC16901DGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 18-Bit Universal Bus Transceiver with Parity Generators/Checkers 64-TSSOP -40 to 85 光电二极管 逻辑集成电路 |
| 文件： | 总9页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCAS276A − NOVEMBER 1993 − REVISED JULY 1995
DGG PACKAGE
(TOP VIEW)
D Member of the Texas Instruments
Widebus+ Family
D EPIC (Enhanced-Performance Implanted
D UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
1CLKENAB
LEAB
CLKAB
1ERRA
1APAR
GND
1CLKENBA
LEBA
CLKBA
1ERRB
1BPAR
GND
1B1
1B2
1B3
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CMOS) Submicron Process
2
3
4
5
6
D Simultaneously Generates and Checks
1A1
1A2
1A3
7
Parity
8
D Option to Select Generate Parity and Check
or Feed-Through Data/Parity in A-to-B or
B-to-A Directions
9
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CC
CC
1A4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
2A5
1B4
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
2B5
D Distributed V
and GND Pin Configuration
Minimizes High-Speed Switching Noise
CC
D Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Packaged in Thin Shrink Small-Outline
(DGG) Package
description
V
V
CC
CC
2A6
2A7
2A8
GND
2B6
2B7
2B8
GND
2BPAR
2ERRB
OEBA
ODD/EVEN
2CLKENBA
This 18-bit (dual-octal) noninverting registered
transceiver is designed for 2.7-V to 3.6-V V
operation.
CC
The SN74ALVC16901 is a dual 9-bit to dual 9-bit
parity transceiver with registers. The device can
operate as a feed-through transceiver or it can
generate/check parity from the two 8-bit data
buses in either direction.
2APAR
2ERRA
OEAB
SEL
2CLKENAB
The SN74ALVC16901 features independent
clock (CLKAB or CLKBA), latch-enable (LEAB or
LEBA), and dual 9-bit clock-enable (CLKENAB or
CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select (ODD/EVEN) inputs and separate
error-signal (ERRA or ERRB) outputs for checking parity. The direction of data flow is controlled by OEAB and
OEBA. When SEL is low, the parity functions are enabled. When SEL is high, the parity functions are disabled
and the device acts as an 18-bit registered transceiver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVC16901 is available in TI’s thin shrink small-outline (DGG) package, which provides twice the I/O
pin count and functionality of standard small-outline packages in the same printed-circuit-board area.
The SN74ALVC16901 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+, EPIC, and UBT are trademarks of Texas Instruments Incorporated.
ꢖꢓ ꢙ ꢜꢑ ꢇ ꢐꢏ ꢙ ꢁ ꢜ ꢄꢐꢄ ꢝꢞ ꢟ ꢠꢡ ꢢ ꢣꢤ ꢝꢠꢞ ꢝꢥ ꢦꢧ ꢡ ꢡ ꢨꢞꢤ ꢣꢥ ꢠꢟ ꢩꢧꢪ ꢫꢝꢦ ꢣꢤ ꢝꢠꢞ ꢬꢣ ꢤꢨ ꢭ
ꢖꢡ ꢠ ꢬꢧꢦ ꢤ ꢥ ꢦ ꢠꢞ ꢟꢠ ꢡ ꢢ ꢤ ꢠ ꢥ ꢩꢨ ꢦ ꢝꢟ ꢝꢦꢣ ꢤꢝ ꢠꢞꢥ ꢩꢨ ꢡ ꢤꢮ ꢨ ꢤꢨ ꢡ ꢢꢥ ꢠꢟ ꢐꢨꢯ ꢣꢥ ꢏꢞꢥ ꢤꢡ ꢧꢢ ꢨꢞꢤ ꢥ
ꢥ ꢤ ꢣ ꢞꢬ ꢣ ꢡꢬ ꢰ ꢣ ꢡꢡ ꢣ ꢞ ꢤꢱꢭ ꢖꢡ ꢠ ꢬꢧꢦ ꢤꢝꢠꢞ ꢩꢡ ꢠꢦ ꢨꢥ ꢥꢝ ꢞꢲ ꢬꢠꢨ ꢥ ꢞꢠꢤ ꢞꢨ ꢦꢨ ꢥꢥ ꢣꢡ ꢝꢫ ꢱ ꢝꢞꢦ ꢫꢧꢬ ꢨ
ꢤ ꢨ ꢥ ꢤꢝ ꢞꢲ ꢠꢟ ꢣ ꢫꢫ ꢩꢣ ꢡ ꢣ ꢢ ꢨ ꢤ ꢨ ꢡ ꢥ ꢭ
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢇ ꢈ ꢉꢊ ꢋꢈ
ꢈꢌ ꢍꢎꢏ ꢐ ꢑ ꢁ ꢏꢆ ꢒꢓ ꢀꢄꢅ ꢎꢑ ꢀ ꢐꢓ ꢄꢁ ꢀꢇ ꢒꢏ ꢆ ꢒ ꢓ
ꢔꢏ ꢐ ꢕ ꢖꢄ ꢓ ꢏꢐ ꢗ ꢘꢒ ꢁꢒ ꢓꢄꢐꢙ ꢓꢀ ꢚꢇ ꢕꢒ ꢇꢛ ꢒꢓꢀ
SCAS276A − NOVEMBER 1993 − REVISED JULY 1995
block diagram
LEAB
2
1CLKENAB,
2CLKENAB
CLKAB
OEAB
OEBA
1B1−1B8
1BPAR
1A1−1A8
18-Bit
Storage
18
18
1APAR
1ERRB
A-Port
Parity
Generate
and
Check
B Data
B-Port
Parity
Generate
and
Check
A Data
1ERRA
2B1−2B8
2BPAR
2A1−2A8
2APAR
18
18
18-Bit
Storage
2ERRA
2ERRB
ODD/EVEN
SEL
CLKBA
2
1CLKENBA
2CLKENBA
LEBA
†
FUNCTION TABLE
INPUTS
OUTPUT
B
Z
L
CLKENAB OEAB
LEAB
CLKAB
A
X
L
X
X
X
H
L
H
L
L
L
L
L
L
L
X
H
H
L
X
X
X
X
↑
↑
L
H
X
L
H
‡
B
0
L
L
L
L
H
X
X
H
‡
§
L
L
B
0
0
L
L
H
B
†
‡
§
A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA,
LEBA, and CLKENBA.
Output level before the indicated steady-state input conditions were
established
Output level before the indicated steady-state input conditions were
established, provided that CLKAB was low before LEAB went low
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCAS276A − NOVEMBER 1993 − REVISED JULY 1995
PARITY-ENABLE FUNCTION TABLE
OPERATION OR FUNCTION
INPUTS
SEL OEBA OEAB
L
L
H
L
L
H
H
L
Parity is checked on port A and is generated on port B.
Parity is checked on port B and is generated on port A.
Parity is checked on port B and port A.
L
H
L
L
Parity is generated on port A and B if device is in FF mode.
H
H
H
H
L
L
Q
Q
Q
data to B, Q data to A
B
A
B
A
Parity functions are
disabled; device acts as a
standard 18-bit registered
transceiver.
L
H
L
data to A
data to B
H
H
H
Isolation
PARITY FUNCTION TABLE
INPUTS
OUTPUTS
BPAR
Σ OF INPUTS Σ OF INPUTS
APAR BPAR APAR
SEL OEBA OEAB ODD/EVEN
ERRA
ERRB
A1−A8 = H
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
N/A
B1−B8 = H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
N/A
L
L
N/A
N/A
N/A
N/A
L
N/A
N/A
N/A
N/A
L
H
L
Z
Z
Z
Z
H
L
N/A
L
L
H
L
L
L
N/A
H
L
L
N/A
H
H
Z
Z
Z
Z
L
H
H
H
H
H
L
L
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
N/A
N/A
N/A
N/A
N/A
L
N/A
N/A
N/A
N/A
H
L
L
N/A
L
H
L
L
N/A
H
L
L
L
L
N/A
H
H
H
Z
Z
Z
Z
L
H
H
H
H
L
H
H
H
H
H
H
H
H
L
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
N/A
N/A
N/A
N/A
N/A
L
N/A
N/A
N/A
N/A
H
L
N/A
L
H
H
L
L
L
N/A
H
H
L
N/A
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
N/A
N/A
N/A
N/A
N/A
L
Z
Z
Z
Z
H
L
N/A
N/A
N/A
N/A
Z
L
N/A
L
L
H
H
L
L
N/A
H
H
L
N/A
H
L
H
H
H
H
H
H
H
H
L
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 8
1, 3, 5, 7
N/A
L
Z
H
L
L
L
L
Z
Z
L
H
H
Z
L
Z
L
L
H
H
Z
H
L
Z
H
L
H
H
H
H
L
L
L
Z
Z
L
L
Z
H
H
L
Z
H
H
L
H
H
Z
Z
H
H
Z
Z
†
†
N/A
N/A
N/A
N/A
PE
PO
Z
Z
PE
PO
Z
Z
‡
‡
L
L
H
N/A
N/A
†
‡
Parity output is set to the level so that the specific bus side is set to even parity.
Parity output is set to the level so that the specific bus side is set to odd parity.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢇ ꢈ ꢉꢊ ꢋꢈ
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ꢔꢏ ꢐ ꢕ ꢖꢄ ꢓ ꢏꢐ ꢗ ꢘꢒ ꢁꢒ ꢓꢄꢐꢙ ꢓꢀ ꢚꢇ ꢕꢒ ꢇꢛ ꢒꢓꢀ
SCAS276A − NOVEMBER 1993 − REVISED JULY 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
I
Input voltage range, V (I/O ports) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50 mA
50 mA
100 mA
OK
O
O
CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
Maximum power dissipation at T = 55°C (in still air) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
A
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 4)
MIN
2.3
1.7
2
MAX
UNIT
V
V
Supply voltage
3.6
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
High-level input voltage
V
V
IH
0.7
0.8
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
V
V
I
CC
Output voltage
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3 V
= 2.7 V
= 3 V
−12
−12
−24
12
I
High-level output current
Low-level output current
mA
mA
OH
= 2.3 V
= 2.7 V
= 3 V
12
I
OL
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
ns/V
T
A
−40
85
°C
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCAS276A − NOVEMBER 1993 − REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= −40°C to 85°C
A
†
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
V −0.2
CC
TYP
MAX
I
I
= −100 µA
MIN to MAX
2.3 V
OH
= −6 mA,
V
IH
V
IH
V
IH
V
IH
V
IH
= 1.7 V
= 1.7 V
= 2 V
2
OH
2.3 V
1.7
2.2
2.4
2
V
V
OH
2.7 V
I
= −12 mA
OH
= 2 V
3 V
I
I
I
= −24 mA,
= 100 µA
= 6 mA,
= 2 V
3 V
OH
OL
OL
MIN to MAX
2.3 V
0.2
0.4
0.7
0.4
0.55
5
V
IL
V
IL
V
IL
V
IL
= 0.7 V
= 0.7 V
= 0.8 V
= 0.8 V
2.3 V
V
V
OL
I
= 12 mA
= 24 mA,
OL
OL
2.7 V
I
3 V
I
I
V = V
CC
or GND
3.6 V
µA
I
I
V = 0.7 V
45
−45
75
I
2.3 V
3 V
V = 1.7 V
I
V = 0.8 V
I
µA
I(hold)
V = 2 V
I
−75
V = 0 to 3.6 V
3.6 V
3.6 V
3.6 V
500
10
I
‡
I
I
V
= V or GND
O CC
or GND,
µA
µA
OZ
V = V
CC
I = 0
O
40
CC
I
V
= 3 V to 3.6 V,
One input at V − 0.6 V,
CC
CC
Other inputs at V
nI
CC
750
µA
or GND
CC
or GND
C
C
C
Control inputs V = V
CC
3.3 V
3.3 V
3.3 V
3
7.5
6
pF
pF
pF
i
I
A or B ports
Output ports
V
= V
or GND
or GND
io
o
O
O
CC
V
= V
CC
†
‡
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
For I/O ports, the paramter I includes the input-leakage current.
OZ
timing requirements over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted) (see Figure 1)
V = 2.5 V
CC
0.2 V
V = 3.3 V
CC
0.3 V
V
CC
= 2.7 V
UNIT
MIN
MAX
MIN
0
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
0
3
125
125
0
3
125
MHz
ns
clock
CLK↑
3
w
LE high
3
3
3
APAR or BPAR before CLK↑
CLKEN before CLK↑
APAR or BPAR before LE↓
APAR or BPAR after CLK↑
CLKEN after CLK↑
APAR or BPAR after LE↓
1.9
2.1
1.4
0.4
0.5
0.9
2
1.7
1.7
1.2
0.5
0.7
0.9
2.1
1.3
0.4
0.5
1.1
t
Setup time
Hold time
ns
ns
su
h
t
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢇ ꢈ ꢉꢊ ꢋꢈ
ꢈꢌ ꢍꢎꢏ ꢐ ꢑ ꢁ ꢏꢆ ꢒꢓ ꢀꢄꢅ ꢎꢑ ꢀ ꢐꢓ ꢄꢁ ꢀꢇ ꢒꢏ ꢆ ꢒ ꢓ
ꢔꢏ ꢐ ꢕ ꢖꢄ ꢓ ꢏꢐ ꢗ ꢘꢒ ꢁꢒ ꢓꢄꢐꢙ ꢓꢀ ꢚꢇ ꢕꢒ ꢇꢛ ꢒꢓꢀ
SCAS276A − NOVEMBER 1993 − REVISED JULY 1995
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figures 1 and 2)
V
= 2.5 V
V
= 3.3 V
CC
0.2 V
CC
0.3 V
V
= 2.7 V
MAX
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MIN
MAX
f
max
125
1.5
2.5
1.5
2.5
2
125
125
1
MHz
A or B
A or B
B or A
5.8
9.5
6.3
10.3
9.3
8.9
6.7
7
4.8
7.6
5.2
8.7
7.9
7.6
5.9
5.8
4.4
6.7
4.7
7.5
6.8
6.5
5.1
5.1
BPAR or APAR
BPAR or APAR
ERRA or ERRB
ERRA or ERRB
BPAR or APAR
BPAR or APAR
A or B
2
APAR or BPAR
APAR or BPAR
ODD/EVEN
ODD/EVEN
SEL
1
2
1.5
1.5
1
2
1.5
1.5
CLKAB or CLKBA
1
BPAR or APAR
parity feedthrough
CLKAB or CLKBA
CLKAB or CLKBA
2
3
7.7
6.3
8.7
1.5
2
5.6
7.7
t
pd
ns
BPAR or APAR
parity generated
10.8
CLKAB or CLKBA
LEAB or LEBA
ERRA or ERRB
A or B
3
11.1
6.6
8.9
5.5
2
1
7.9
4.8
1.5
BPAR or APAR
parity feedthrough
LEAB or LEBA
LEAB or LEBA
2
3
7.3
6
1.5
2
5.3
7.4
BPAR or APAR
parity generated
10.4
8.3
LEAB or LEBA
OEAB or OEBA
OEAB or OEBA
OEAB or OEBA
OEAB or OEBA
SEL
ERRA or ERRB
B, BPAR or A, APAR
B, BPAR or A, APAR
ERRA or ERRB
3
1.5
2
10.5
6.8
6.3
6.7
7.5
7.2
6.6
8.5
6.1
5.2
5.5
6.5
6.5
5.4
2
1
7.5
5.3
4.9
4.9
5.7
5.5
4.9
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
en
dis
en
dis
en
dis
1.5
1
1.5
2
ERRA or ERRB
1
ERRA or ERRB
1.5
2
1
ERRA or ERRB
1.5
SEL
operating characteristics, T = 25°C
A
V
CC
= 2.5 V
V
CC
= 3.3 V
0.2 V
TYP
22
0.3 V
TYP
27
PARAMETER
TEST CONDITIONS
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance
C
= 50 pF,
L
f = 10 MHz
pF
pd
5
8
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇꢈ
ꢉ
ꢊ
ꢋꢈ
ꢈ
ꢌ
ꢍ
ꢎ
ꢏ
ꢐ
ꢑ
ꢁ
ꢏ
ꢆꢒ
ꢓꢀ
ꢄ
ꢅ
ꢎ
ꢑ
ꢀ
ꢐ
ꢓꢄ
ꢁ
ꢀ
ꢇ
ꢒ
ꢏꢆ
ꢒ
ꢓ
ꢔ
ꢏ
ꢐ
ꢕ
ꢖ
ꢄ
ꢓ
ꢏ
ꢐ
ꢗ
ꢘ
ꢒ
ꢁ
ꢒ
ꢓ
ꢄ
ꢐ
ꢙ
ꢓ
ꢀ
ꢚ
ꢇ
ꢕ
ꢒ
ꢇ
ꢛ
ꢒ
ꢓ
ꢀ
SCAS276A − NOVEMBER 1993 − REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V " 0.2 V
CC
4.6 V
TEST
S1
S1
t
Open
4.6 V
GND
500 Ω
Open
GND
pd
/t
From Output
Under Test
t
PLZ PZL
/t
PHZ PZH
t
C
= 50 pF
L
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
1.2 V
2.3 V
0 V
Input
2.3 V
1.2 V
1.2 V
Timing
Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
2.3 V
Data
Input
2.3 V
0 V
1.2 V
1.2 V
Output
0 V
Control
(low-level
enabling)
1.2 V
1.2 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
t
PLZ
2.3 V
Output
Waveform 1
S1 at 4.6 V
2.3 V
0 V
1.2 V
Input
V
+ 0.3 V
− 0.3 V
1.2 V
1.2 V
OL
V
OL
OH
(see Note B)
t
PHZ
t
PLH
t
PZH
PHL
Output
Waveform 2
S1 at GND
V
V
V
OH
V
OH
1.2 V
Output
1.2 V
1.2 V
(see Note B)
0 V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, Z = 50 Ω, t v2.5 ns, t v2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢇ ꢈ ꢉꢊ ꢋꢈ
ꢈꢌ ꢍꢎꢏ ꢐ ꢑ ꢁ ꢏꢆ ꢒꢓ ꢀꢄꢅ ꢎꢑ ꢀ ꢐꢓ ꢄꢁ ꢀꢇ ꢒꢏ ꢆ ꢒ ꢓ
ꢔꢏ ꢐ ꢕ ꢖꢄ ꢓ ꢏꢐ ꢗ ꢘꢒ ꢁꢒ ꢓꢄꢐꢙ ꢓꢀ ꢚꢇ ꢕꢒ ꢇꢛ ꢒꢓꢀ
SCAS276A − NOVEMBER 1993 − REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
V
= 2.7 V AND 3.3 V " 0.3 V
CC
6 V
TEST
S1
S1
t
Open
6 V
pd
/t
Open
GND
500 Ω
From Output
Under Test
t
PLZ PZL
/t
t
GND
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
1.5 V
2.7 V
0 V
Input
1.5 V
1.5 V
2.7 V
0 V
Timing
Input
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
2.7 V
0 V
Data
Input
2.7 V
0 V
1.5 V
1.5 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
t
PLZ
3 V
Output
Waveform 1
S1 at 6 V
2.7 V
0 V
1.5 V
Input
V
+ 0.3 V
− 0.3 V
1.5 V
1.5 V
OL
V
OL
OH
(see Note B)
t
PHZ
t
PLH
t
PZH
PHL
Output
Waveform 2
S1 at GND
V
V
V
OH
V
OH
1.5 V
Output
1.5 V
1.5 V
(see Note B)
0 V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, Z = 50 Ω, t v2.5 ns, t v2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
andt
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
PHL
are the same as t
.
en
are the same as t .
pd
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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