SN74ALVC3631-15PCB [TI]
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES;
| 型号： | SN74ALVC3631-15PCB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES |
| 文件： | 总28页 (文件大小：438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
Output-Ready and AE Flags Synchronized
by CLKB
Clocked FIFO Buffering Data From Port A
to Port B
Low-Power 0.8-µm Advanced CMOS
Technology
Synchronous Read-Retransmit Capability
Mailbox Register in Each Direction
Supports Clock Frequencies up to 100 MHz
Fast Access Times of 6.5 ns
Programmable Almost-Full (AF) and
Almost-Empty (AE) Flags
Pin-to-Pin Compatible With 5-V Operating
SN74ACT3631, SN74ACT3641, and
SN74ACT3651
Microprocessor Interface Control Logic
Package Options Include 120-Pin Thin
Quad Flat (PCB) and 132-Pin Plastic Quad
Flat (PQ) Packages
Input-Ready and AF Flags Synchronized by
CLKA
description
The SN74ALVC3631, SN74ALVC3641, and SN74ALVC3651 are high-speed, low-power, CMOS, synchronous
FIFO memories that support clock frequencies up to 100 MHz and have read access times as fast as 6.5 ns.
The 512 × 36, 1024 × 36, and 2048 × 36 dual-port SRAM FIFOs buffer data from port A to port B. The FIFO
memories have retransmit capability, which allows previously read data to be accessed again. The FIFOs have
flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate
when a selected number of words is stored in memory. Communication between each port takes place with two
36-bit mailbox registers. Each mailbox register has a flag that signals when new mail has been stored. Two or
more devices are used in parallel to create wider data paths. Expansion also is possible in word depth.
The SN74ALVC3631/41/51 are synchronous FIFOs, which means each port employs a synchronous interface.
All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock
by enable signals. The continuous clocks for each port are independent of one another and can be
asynchronous or coincident. The enables for each port are arranged to provide a simple interface between
microprocessors and/or buses with synchronous control.
The input-ready (IR) flag and almost-full (AF) flag of the FIFOs are two-stage, synchronized to CLKA. The
output-ready (OR) flag and almost-empty (AE) flag of the FIFOs are two-stage, synchronized to CLKB. Offset
values for AF and AE are programmed from port A or through a serial input.
The SN74ALVC3631/41/51 are characterized for operation from 0°C to 70°C.
For more information on this device family, see the following application reports:
FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering
(literature number SCAA009)
FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control
(literature number SCAA007)
Metastability Performance of Clocked FIFOs (literature number SCZA004)
FIFO Architecture, Functions, and Applications (literature number SCAA042)
Optimizing DSP-Based Digital Filters With Application-Specific FIFOs (literature number SCAA021)
FIFO Memories: Surface-Mount Packages for PCMCIA Applications (literature number SDMA001A)
Interfacing TI Clocked FIFOs with TI Floating-Point DSPs (literature number SCAA005A)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
PCB PACKAGE
(TOP VIEW)
A35
A34
A33
A32
1
2
3
4
5
6
7
8
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
V
A31
CC
A30
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
CC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
V
CC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
V
CC
B15
B14
B13
B12
GND
V
A12
CC
NC – No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
†
PQ PACKAGE
(TOP VIEW)
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1 132 130 128
131
129
126 124 122 120 118
127 125 123
121 119
117
116
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
NC
NC
A35
A34
A33
A32
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
V
CC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
V
CC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
98
97
V
CC
96
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
95
94
93
92
91
V
CC
90
B15
B14
B13
B12
GND
NC
89
88
87
86
V
CC
85
A12
NC
84
NC
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
NC – No internal connection
†
Uses Yamaichi socket IC51-1324-828
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
functional block diagram
MBF1
Mail1
Register
CLKA
CSA
W/RA
ENA
Port-A
Control
Logic
MBA
512 × 36 or
1024 × 36 or
†
2048 × 36
SRAM
Reset
Logic
RST
RTM
RFM
36
Write
Read
Pointer
Pointer
A0–A35
B0–B35
Status-Flag
IR
AF
OR
AE
Logic
Flag-Offset
Register
FS0/SD
FS1/SEN
CLKB
CSB
W/RB
ENB
Port-B
Control
Logic
10
Mail2
Register
MBB
MBF2
†
512 × 36 for the SN74ALVC3631, 1024 × 36 for the SN74ALVC3641, and 2048 × 36 for the SN74ALVC3651
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
Terminal Functions
TERMINAL
NAME
I/O
I/O
O
DESCRIPTION
A0–A35
AE
Port-A data. The 36-bit bidirectional data port for side A.
Almost-emptyflag. Programmable flag synchronized to CLKB. AE is low when the number of words in the FIFO is less
than or equal to the value in the almost-empty offset register (X).
Almost-full flag. Programmable flag synchronized to CLKA. AF is low when the number of empty locations in the FIFO
is less than or equal to the value in the almost-full offset register (Y).
AF
O
I/O
I
B0–B35
CLKA
Port-B data. The 36-bit bidirectional data port for side B.
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
or coincident to CLKB. IR and AF are synchronous to the low-to-high transition of CLKA.
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
or coincident to CLKA. OR and AE are synchronous to the low-to-high transition of CLKB.
CLKB
CSA
CSB
I
I
I
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The
A0–A35 outputs are in the high-impedance state when CSA is high.
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The
B0–B35 outputs are in the high-impedance state when CSB is high.
ENA
ENB
I
I
Port-A master enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.
Port-B master enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.
Flag-offset select 1/serial enable, flag-offset select 0/serial data. FS1/SEN and FS0/SD are dual-purpose inputs used
for flag-offset-register programming. During a device reset, FS1/SEN and FS0/SD select the flag-offset programming
method. Three offset-register programming methods are available: automatically load one of two preset values,
parallel load from port A, and serial load.
FS1/SEN,
FS0/SD
I
When serial load is selected for flag-offset-register programming, FS1/SEN is used as an enable synchronous to the
low-to-high transition of CLKA. When FS1/SEN is low, a rising edge on CLKA loads the bit present on FS0/SD into
the X-and Y-offset registers. The number of bit writes required to program the offset registers is 22. The first bit write
stores the Y-register MSB and the last bit write stores the X-register LSB.
Input-ready flag. IR is synchronized to the low-to-high transition of CLKA. When IR is low, the FIFO is full and writes
to its array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the
point of the retransmit data and prevents further writes. IR is set low during reset and is set high after reset.
IR
O
I
MBA
MBB
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0–B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects
FIFO data for output.
I
Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. MBF1
is set high by a low-to-high transition of CLKB when a port-B read is selected and MBB is high. MBF1 is set high by
a reset.
O
O
O
MBF1
MBF2
OR
Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. MBF2
is set high by a low-to-high transition of CLKA when a port-A read is selected and MBA is high. MBF2 is set high by
a reset.
Output-ready flag. OR is synchronized to the low-to-high transition of CLKB. When OR is low, the FIFO is empty and
reads are disabled. Ready data is present in the output register of the FIFO when OR is high. OR is forced low during
the reset and goes high on the third low-to-high transition of CLKB after a word is loaded to empty memory.
Read from mark. When the FIFO is in retransmit mode, a high on RFM enables a low-to-high transition of CLKB to
reset the read pointer to the beginning retransmit location and output the first selected retransmit data.
RFM
RST
I
I
Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur
while RST is low. The low-to-high transition of RST latches the status of FS0 and FS1 for AF and AE offset selection.
Retransmit mode. When RTM is high and valid data is present in the FIFO output register (OR is high), a low-to-high
transitionofCLKBselectsthedataforthebeginningofaretransmitandputstheFIFOinretransmitmode. Theselected
word remains the initial retransmit point until a low-to-high transition of CLKB occurs while RTM is low, taking the FIFO
out of retransmit mode.
RTM
I
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for
a low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/RA is high.
I
I
W/RA
W/RB
Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for
a low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W/RB is low.
detailed description
reset
The SN74ALVC3631/41/51 are reset by taking the reset (RST) input low for at least four port-A clock (CLKA)
and four port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks.
A reset initializes the memory-read and-write pointers and forces the IR flag low, the OR flag high, the AE flag
low, and the AF flag high. Resetting the device also forces the mailbox flags (MBF1, MBF2) high. After a FIFO
is reset, IR is set high after at least two clock cycles to begin normal operation. A FIFO must be reset after power
up before data is written to its memory.
almost-empty flag and almost-full flag offset programming
Two registers in the SN74ALVC3631/41/51 are used to hold the offset values for the AE and AF flags. The AE
flag offset register is labeled X, and the AF flag offset register is labeled Y. The offset registers can be loaded
with a value in three ways: one of two preset values is loaded into the offset registers, parallel load from port
A, or serial load. The offset-register-programming mode is chosen by the flag select (FS1, FS0) inputs during
a low-to-high transition on RST (see Table 1).
Table 1. Flag Programming
†
FS1
H
FS0
H
RST
X AND Y REGISTERS
↑
↑
↑
↑
Serial load
H
L
64
8
L
H
L
L
Parallel load from port A
†
X register holds the offset for AE; Y register holds the
offset for AF.
preset values
If a preset value of 8 or 64 is chosen by FS1 and FS0 at the time of an RST low-to-high transition according to
Table 1, the preset value is automatically loaded into the X and Y registers. No other device initialization is
necessary to begin normal operation, and the IR flag is set high after two low-to-high transitions on CLKA.
parallel load from port A
To program the X and Y registers from port A, the device is reset with FS0 and FS1 low during the low-to-high
transition of RST. After this reset is complete, the IR flag is set high after two low-to-high transitions on CLKA.
The first two writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X.
Each offset register of the SN74ALVC3631/41/51 uses port-A inputs (A10–A0). The highest number input is
used as the most-significant bit of the binary number in each case. Each register value can be programmed from
1 to 508 (SN74ALVC3631), 1 to 1020 (SN74ALVC3641), and 1 to 2044 (SN74ALVC3651). After both offset
registers are programmed from port A, subsequent FIFO writes store data in the SRAM.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
serial load
To program the X and Y registers serially, the device is reset with FS0/SD and FS1/SEN high during the
low-to-high transition of RST. After this reset is complete, the X-and Y-register values are loaded bitwise through
FS0/SD on each low-to-high transition of CLKA that FS1/SEN is low. Eighteen (SN74ALVC3631), twenty
(SN74ALVC3641), and twenty-two (SN74ALVC3651) bit writes are needed to complete the programming. The
first bit write stores the most-significant bit of the Y register and the last bit write stores the least-significant bit
of the X register. Each register value can be programmed from 1 to 508 (SN74ALVC3631), 1 to 1020
(SN74ALVC3641), and 1 to 2044 (SN74ALVC3651).
When the option is chosen to program the offset registers serially, the IR flag remains low until all register bits
are written. The IR flag is set high by the low-to-high transition of CLKA after the last bit is loaded, to allow normal
FIFO operation.
FIFO write/read operation
The state of the port-A data (A0–A35) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (W/RA). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is
high. The A0–A35 outputs are active when both CSA and W/RA are low.
Data is loaded into the FIFO from the A0–A35 inputs on a low-to-high transition of CLKA when CSA and the
port-A mailbox select (MBA) are low, W/RA, the port-A enable (ENA), and the IR flag are high (see Table 2).
Writes to the FIFO are independent of any concurrent FIFO reads.
Table 2. Port-A Enable Function Table
CSA W/RA ENA
MBA CLKA
A0–A35 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, mail2 register
Active, mail2 register
Active, mail2 register
Active, mail2 register
PORT FUNCTION
H
L
L
L
L
L
L
L
X
H
H
H
L
X
L
X
X
L
X
X
↑
None
None
FIFO write
Mail1 write
None
H
H
L
H
L
↑
X
↑
L
H
L
L
None
L
H
H
X
↑
None
L
H
Mail2 read (set MBF2 high)
The port-B control signals are identical to those of port A, with the exception that the port-B write/read select
(W/RB) is the inverse of the W/RA. The state of the port-B data (B0–B35) outputs is controlled by the port-B
chip select (CSB) and W/RB. The B0–B35 outputs are in the high-impedance state when either CSB is high or
W/RB is low. The B0–B35 outputs are active when CSB is low and W/RB is high.
Data is read from the FIFO to its output register on a low-to-high transition of CLKB when CSB and MBB are
low, W/RB, ENB, andtheORflagarehigh(seeTable3). ReadsfromtheFIFOareindependentofanyconcurrent
FIFO writes.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
Table 3. Port-B Enable Function Table
CSB W/RB ENB
MBB CLKB
B0–B35 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, FIFO output register
Active, FIFO output register
Active, mail1 register
PORT FUNCTION
H
L
L
L
L
L
L
L
X
L
X
L
X
X
L
X
X
↑
None
None
None
L
H
H
L
L
H
L
↑
Mail2 write
None
H
H
H
H
X
↑
H
L
L
FIFO read
H
H
X
↑
None
H
Active, mail1 register
Mail1 read (set MBF1 high)
The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only
for enabling write and read operations and are not related to high-impedance control of the data outputs. If a
port enable is low during a clock cycle, the port-chip select and write/read select can change states during the
setup- and hold-time window of the cycle.
When OR is low, the next data word is sent to the FIFO output register automatically by the CLKB low-to-high
transition that sets OR high. When OR is high, an available data word is clocked to the FIFO output register only
when a FIFO read is selected by CSB, W/RB, ENB, and MBB.
synchronized FIFO flags
Each FIFO flag is synchronized to its port clock through at least two flip-flop stages. This is done to improve the
flag’s reliability by reducing the probability of metastable events on their outputs when CLKA and CLKB operate
asynchronously with one another. OR and AE are synchronized to CLKB. IR and AF are synchronized to CLKA.
Table 4 shows the relationship of each flag to the number of words stored in memory.
Table 4. FIFO Flag Operation
SYNCHRONIZED SYNCHRONIZED
NUMBER OF WORDS
TO CLKB
TO CLKA
IN FIFO
OR
AE
L
AF
IR
H
H
H
H
L
0
L
H
H
H
L
1 to X
H
H
H
H
L
§
(X + 1) to [D – (Y + 1)]
H
H
H
§
(D – Y) to 2047
§
D
L
†
‡
X is the almost-empty offset for AE. Y is the almost-full offset for AF.
WhenawordispresentintheFIFOoutputregister, itspreviousmemory
location is free.
D = 512 for the SN74ALVC3631, D = 1024 for the SN74ALVC3641, and
D = 2048 for the SN74ALVC3651
§
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
output-ready flag
The OR flag of a FIFO is synchronized to CLKB. When OR is high, new data is present in the FIFO output
register. When OR is low, the previous data word is present in the FIFO output register and attempted FIFO
reads are ignored.
A FIFO read pointer is incremented each time a new word is clocked to its output register. When a word is written
to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of CLKB; therefore, an OR
flag is low if a word in memory is the next data to be sent to the FIFO output register and three CLKB cycles
have not elapsed since the word was written. The output-ready flag of the FIFO remains low until the third
low-to-high transition of CLKB occurs, simultaneously forcing the OR flag high and shifting the word to the FIFO
output register.
A low-to-high transition on CLKB begins the first synchronization cycle of a write if the clock transition occurs
at time t
cycle (see Figure 6).
, or greater, after the write. Otherwise, the subsequent CLKB cycle can be the first synchronization
sk(1)
input-ready flag
The IR flag of a FIFO is synchronized to the CLKA. When the IR flag is high, a memory location is free in the
SRAM to write new data. No memory locations are free when the IR flag is low and attempted writes to the FIFO
are ignored.
Each time a word is written to a FIFO, its write pointer is incremented. When a word is read from a FIFO, its
previous memory location can be written in a minimum of three cycles of CLKA; therefore, an IR flag is low if
less than two cycles of CLKA have elapsed since the next memory write location has been read. The second
low-to-high transition on CLKA after the read sets the IR flag high, and data can be written in the following cycle.
A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs
at time t
cycle (see Figure 7).
, or greater, after the read. Otherwise, the subsequent CLKA cycle can be the first synchronization
sk(1)
almost-empty flag
The AE flag of a FIFO is synchronized to CLKB. The almost-empty state is defined by the contents of register
X. This register is loaded with a preset value during a FIFO reset, programmed from port A, or programmed
serially (see almost-empty flag and almost-full flag offset programming). The AE flag is low when the FIFO
contains X or fewer words and is high when the FIFO contains (X + 1) or more words. A data word present in
the FIFO output register has been read from memory.
Two low-to-high transitions of CLKB are required after a FIFO write for the AE flag to reflect the new level of
fill; therefore, the AE flag of a FIFO containing (X + 1) or more words remains low if two cycles of CLKB have
not elapsed since the write that filled the memory to the (X + 1) level. An AE flag is set high by the second
low-to-high transition of CLKB after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition
ofCLKBbeginsthefirstsynchronizationcycleifitoccursattimet
to (X + 1) words. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle (see Figure 8).
, orgreater, afterthewritethatfillstheFIFO
sk(2)
9
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almost-full flag
The AF flag of a FIFO is synchronized to the port clock that writes data to its array (CLKA). The almost-full state
is defined by the contents of register Y. This register is loaded with a preset value during a FIFO reset,
programmed from port A, or programmed serially (see almost-empty flag and almost-full flag offset
programming). The AF flag is low when the number of words in the FIFO is greater than or equal to D – Y, where
D = FIFO depth (512 for SN74ALVC3631, 1024 for SN74ALVC3641, and 2048 for SN74ALVC3651). The AF
flag is high when the number of words in the FIFO is less than or equal to [D – (Y + 1)]. A data word present
in the FIFO output register has been read from memory.
Two low-to-high transitions of CLKA are required after a FIFO read for its AF flag to reflect the new level of fill.
Therefore, the AF flag of a FIFO containing [D – (Y + 1)] or less words remains low if two cycles of CLKA have
not elapsed since the read that reduced the number of words in memory to [D – (Y + 1)]. An AF flag is set high
by the second low-to-high transition of CLKA after the FIFO read that reduces the number of words in memory
to [D – (Y + 1)]. A low-to-high transition of CLKA begins the first synchronization cycle if it occurs at time t
,
sk(2)
or greater, after the read that reduces the number of words in memory to [D – (Y + 1)]. Otherwise, the
subsequent CLKA cycle can be the first synchronization cycle (see Figure 9).
synchronous retransmit
The synchronous-retransmit feature of the SN74ALVC3631/41/51 allows FIFO data to be read repeatedly,
starting at a user-selected position. The FIFO is first put into retransmit mode (RTM) to select a beginning word
andpreventongoingFIFOwriteoperationsfromdestroyingretransmitdata. Datavectorswithaminimumlength
of three words can retransmit repeatedly, starting at the selected word. The FIFO can be taken out of RTM at
any time without affecting normal device operation.
The FIFO is put in retransmit mode by a low-to-high transition on CLKB when the RTM input is high and OR
is high. This rising CLKB edge marks the data present in the FIFO output register as the first retransmit data.
The FIFO goes out of retransmit mode when RTM goes low (see Figure 10).
When two or more reads have been done past the initial retransmit word, a retransmit is initiated by alow-to-high
transition on CLKB when the read-from-mark (RFM) input is high. This rising CLKB edge shifts the first
retransmit word to the FIFO output register and subsequent reads can begin immediately. Retransmit loops can
be done endlessly while the FIFO is in RTM. RFM must be low during the CLKB rising edge that takes the FIFO
out of retransmit mode.
When the FIFO is put into RTM, it operates with two read pointers. The current read pointer operates normally,
incrementing each time a new word is shifted to the FIFO output register and used by the OR and AE flags. The
shadow read pointer stores the SRAM location at the time the device is put into RTM and does not change until
the device is taken out of RTM. The shadow read pointer is used by the IR and AF flags. Data writes can proceed
while the FIFO is in RTM, but AF is set low by the write that stores (D – Y) words after the first retransmit word.
The IR flag is set low by the Dth write after the first retransmit word.
When the FIFO is in RTM and RFM is high, a rising CLKB edge loads the current read pointer with the shadow
read-pointer value and the OR flag reflects the new level of fill immediately. If the retransmit changes the FIFO
status out of the almost-empty range, up to two CLKB rising edges after the retransmit cycle are needed to
switch AE high (see Figure 11). The rising CLKB edge that takes the FIFO out of retransmit mode shifts the read
pointer used by the IR and AF flags from the shadow to the current read pointer. If the change of read pointer
used by IR and AF should cause one or both flags to transition high, at least two CLKA synchronizing cycles
are needed before the flags reflect the change. A rising CLKA edge after the FIFO is taken out of retransmit
mode is the first synchronizing cycle of IR if it occurs at time t
Figure 12). A rising CLKA edge after the FIFO is taken out of RTM is the first synchronizing cycle of AF if it occurs
, or greater, after the rising CLKB edge (see
sk(1)
at time t
, or greater, after the rising CLKB edge (see Figure 14).
sk(2)
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mailbox registers
Two 36-bit bypass registers pass command and control information between port A and port B. The
mailbox-select(MBA, MBB)inputschoosebetweenamailregisterandaFIFOforaportdata-transferoperation.
A low-to-high transition on CLKA writes A0–A35 data to the mail1 register when a port-A write is selected by
CSA, W/RA, and ENA with MBA high. A low-to-high transition on CLKB writes B0–B35 data to the mail2 register
when a port-B write is selected by CSB, W/RB, and ENB with MBB high. Writing data to a mail register sets its
corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while its mail flag is
low.
When the port-B data (B0–B35) outputs are active, the data on the bus comes from the FIFO output register
when the MBB input is low and from the mail1 register when MBB is high. Mail2 data always is present on the
port-A data (A0–A35) outputs when they are active. The mail1 register flag (MBF1) is set high by a low-to-high
transition on CLKB when a port-B read is selected by CSB, W/RB, and ENB with MBB high. The mail2 register
flag (MBF2) is set high by a low-to-high transition on CLKA when a port-A read is selected by CSA, W/RA, and
ENA with MBA high. The data in a mail register remains intact after it is read and changes only when new data
is written to the register.
CLKA
t
h(RS)
CLKB
t
h(FS)
t
su(RS)
t
su(FS)
RST
FS1, FS0
0,1
t
t
pd(C-IR)
pd(C-IR)
IR
OR
AE
AF
t
pd(C-OR)
t
pd(R-F)
t
t
pd(R-F)
pd(R-F)
MBF1,
MBF2
Figure 1. FIFO Reset Loading X and Y With a Preset Value of Eight
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CLKA
RST
4
t
su(FS)
t
h(FS)
FS1, FS0
t
pd(C-IR)
IR
ENA
t
h(EN)
t
su(EN)
t
h(D)
t
su(D)
A0–A35
AF Offset
(Y)
AE Offset
(X)
First Word Stored in FIFO
NOTE A: CSA= L, W/RA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles.
Figure 2. Programming the AF Flag and AE Flag Offset Values From Port A
CLKA
RST
4
t
pd(C-IR)
IR
FS1/SEN
FS0/SD
t
t
t
t
h(SEN)
h(SP)
h(SEN)
t
t
su(SEN)
t
su(FS)
su(SEN)
t
h(SD)
h(SD)
t
su(FS)
t
t
su(SD)
t
su(SD)
h(FS)
AF Offset
(Y) MSB
AE Offset
(X) LSB
NOTE A: It is not necessary to program offset-register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set high.
Figure 3. Programming the AF Flag and AE Flag Offset Values Serially
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t
c
t
t
w(CLKL)
w(CLKH)
CLKA
IR
High
t
t
t
su(EN)
su(EN)
h(EN)
CSA
t
t
h(EN)
h(EN)
W/RA
MBA
t
t
su(EN)
su(EN)
t
t
h(EN)
h(EN)
t
t
t
t
h(EN)
h(D)
su(EN)
su(EN)
ENA
t
su(D)
A0–A35
No Operation
W1
W2
Figure 4. FIFO Write Cycle
t
c
t
t
w(CLKH)
CLKB
w(CLKL)
OR High
CSB
W/RB
MBB
t
t
t
su(EN)
su(EN)
su(EN)
t
t
t
h(EN)
h(EN)
h(EN)
ENB
No
Operation
t
pd(M-DV)
t
t
dis
a
t
t
a
en
W1
W2
W3
B0–B35
Figure 5. FIFO Read Cycle
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t
c
t
t
w(CLKL)
w(CLKH)
CLKA
Low
CSA
W/RA
High
t
su(EN)
t
t
h(EN)
MBA
ENA
t
su(EN)
h(EN)
High
IR
t
su(D)
t
h(D)
A0–A35
W1
t
t
†
c
t
sk(1)
w(CLKL)
t
w(CLKH)
1
2
t
3
CLKB
OR
t
pd(C-OR)
pd(C-OR)
Old Data in FIFO Output Register
CSB Low
W/RB
High
MBB Low
ENB
t
h(EN)
t
su(EN)
t
a
B0–B35
W1
Old Data in FIFO Output Register
†
t
is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition high and to clock the next word to the FIFO
sk(1)
output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t
OR high and the first word load to the output register can occur one CLKB cycle later than shown.
, then the transition of
sk(1)
Figure 6. OR-Flag Timing and First-Data-Word Fall Through When FIFO Is Empty
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t
c
t
t
w(CLKL)
w(CLKH)
CLKB
Low
CSB
W/RB
MBB
High
Low
t
t
h(EN)
su(EN)
ENB
OR
High
t
a
B0–B35
FIFO Output Register
Next Word From FIFO
†
t
sk(1)
t
c
t
t
w(CLKL)
w(CLKH)
1
2
CLKA
IR
t
t
pd(C-IR)
pd(C-IR)
FIFO Full
CSA
W/RA
MBA
Low
High
t
t
t
h(EN)
su(EN)
t
t
su(EN)
h(EN)
h(D)
ENA
t
su(D)
Write
A0–A35
†
t
is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the time
sk(1)
between the rising CLKB edge and rising CLKA edge is less than t
, then IR can transition high one CLKA cycle later than shown.
sk(1)
Figure 7. IR-Flag Timing and First Available Write When FIFO Is Full
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CLKA
t
h(EN)
t
su(EN)
ENA
†
t
sk(2)
CLKB
AE
1
2
t
t
pd(C-AE)
pd(C-AE)
X Words in FIFO
(X + 1) Words in FIFO
t
h(EN)
t
su(EN)
ENB
†
t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition high in the next CLKB cycle. If the time
sk(2)
between the rising CLKA edge and rising CLKB edge is less than t
, then AE can transition high one CLKB cycle later than shown.
sk(2)
NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L)
Figure 8. Timing for AE When FIFO Is Almost Empty
‡
t
sk(2)
CLKA
ENA
1
2
t
h(EN)
t
su(EN)
t
t
pd(C-AF)
pd(C-AF)
§
(D – Y) Words in FIFO
§
AF
[D – (Y + 1)] Words in FIFO
CLKB
ENB
t
h(EN)
t
su(EN)
‡
§
t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition high in the next CLKA cycle. If the time
sk(2)
between the rising CLKB edge and rising CLKA edge is less than t
sk(2)
D = 512 for the SN74ALVC3631; D = 1024 for the SN74ALVC3641; D = 2048 for the SN74ALVC3651.
, then AF can transition high one CLKA cycle later than shown.
NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = H, MBB = L)
Figure 9. Timing for AF When FIFO Is Almost Full
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CLKB
ENB
t
t
t
t
t
t
su(EN)
h(EN)
su(EN)
su(EN)
h(EN)
h(EN)
t
su(EN)
RTM
RFM
OR
High
t
t
t
a
t
a
a
a
B0–B35
W0
W1
W2
W0
W1
Initiate Retransmit Mode
With W0 as First Word
Retransmit From
Selected Position
End Retransmit
Mode
NOTE A: CSB = L, W/RB = H, MBB = L. No input enables other than RTM and RFM are needed to control retransmit mode or begin a retransmit.
Other enables are shown only to relate retransmit operations to the FIFO output register.
Figure 10. Retransmit Timing Showing Minimum Retransmit Length
CLKB
RTM
1
2
High
t
h(RM)
t
su(RM)
RFM
AE
t
pd(C-AE)
X or Fewer Words From Empty
(X + 1) or More Words From Empty
NOTE A: X is the value loaded in the AE-flag offset register.
Figure 11. AE Maximum Latency When Retransmit Increases the Number of Stored Words Above X
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†
t
sk(1)
CLKA
IR
1
2
t
pd(C-IR)
FIFO Filled to First Retransmit Word
One or More Write Locations Available
CLKB
t
t
h(EN)
su(EN)
RTM
†
t
is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition high in the next CLKA cycle. If the time
sk(1)
between the rising CLKB edge and rising CLKA edge is less than t
, then IR can transition high one CLKA cycle later than shown.
sk(1)
Figure 12. IR Timing From the End of Retransmit Mode When One or More Write Locations Are Available
‡
t
sk(2)
CLKA
AF
1
2
t
pd(C-AE)
§
(D – Y) or More Words Past First Retransmit Word
(Y + 1) or More Write Locations Available
CLKB
t
t
h(EN)
su(EN)
RTM
‡
t
is the minimum time between a rising CLKB edge and a rising CLKA edge for AF to transition high in the next CLKA cycle. If the time
sk(2)
between the rising CLKB edge and rising CLKA edge is less than t
, then AF can transition high one CLKA cycle later than shown.
sk(2)
D = 512 for the SN74ALVC3631; D = 1024 for the SN74ALVC3641; D = 2048 for the SN74ALVC3651.
NOTE A: Y is the value loaded in the AF flag offset register.
§
Figure 13. AF Timing From the End of Retransmit Mode
When (Y + 1) or More Write Locations Are Available
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CLKA
t
h(EN)
t
su(EN)
CSA
W/RA
MBA
ENA
t
h(D)
t
su(D)
A0–A35
W1
CLKB
MBF1
t
t
pd(C-MF)
pd(C-MF)
CSB
W/RB
MBB
ENB
t
h(EN)
t
su(EN)
t
pd(M-DV)
t
dis
t
t
en
pd(C-MR)
B0–B35
W1 (remains valid in mail1 register after read)
FIFO Output Register
Figure 14. Mail1 Register and MBF1 Flag
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CLKB
t
h(EN)
t
su(EN)
CSB
W/RB
MBB
ENB
t
h(D)
t
su(D)
B0–B35
W1
CLKA
MBF2
t
t
pd(C-MF)
pd(C-MF)
CSA
W/RA
MBA
ENA
t
h(EN)
t
su(EN)
t
t
dis
t
en
pd(C-MR)
A0–A35
W1 (remains valid in mail2 register after read)
Figure 15. Mail2 Register and MBF2 Flag
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†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): PCB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
JA
PQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN
3.0
2
TYP
MAX
3.6
+ 0.5
0.8
–4
UNIT
V
V
V
V
Supply voltage
3.3
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
V
CC
V
IH
V
IL
I
I
mA
mA
°C
OH
8
OL
T
A
0
70
electrical characteristics over recommended operating conditions (unless otherwise noted)
‡
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
= 3.0 V,
= 3.0 V,
= 3.6 V,
= 3.6 V,
= 3.6 V,
I
I
= –4 mA
= 8 mA
2.4
OH
CC
CC
CC
CC
CC
OH
0.5
±5
V
OL
OL
I
I
I
V = V
I
or 0
µA
µA
µA
pF
pF
I
CC
V
O
= V
or 0
±5
OZ
CC
CC
V = V
I
– 0.2 V or 0
350
CC
C
C
V = 0,
I
f = 1 MHz
f = 1 MHz
4
8
io
V = 0,
I
control
‡
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
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timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 16)
’ALVC3631-10 ’ALVC3631-15 ’ALVC3631-20
’ALVC3641-10 ’ALVC3641-15 ’ALVC3641-20
’ALVC3651-10 ’ALVC3651-15 ’ALVC3651-20
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
f
t
t
t
Clock frequency, CLKA or CLKB
Clock cycle time, CLKA or CLKB
Pulse duration, CLKA and CLKB high
Pulse duration, CLKA and CLKB low
100
66.7
50
MHz
ns
clock
10
4
15
6
20
8
c
ns
w(CH)
w(CL)
4
6
8
ns
Setup time,
t
t
2.5
3.5
3.5
5
4.5
6
ns
ns
su(D)
A0–A35 before CLKA↑ and B0–B35 before CLKB↑
Setup time, CSA, W/RA, ENA, and MBA before CLKA↑;
CSB, W/RB, ENB, MBB, RTM, and RFM before CLKB↑
su(EN)
†
t
t
t
t
t
Setup time, RST low before CLKA↑ or CLKB↑
Setup time, FS0 and FS1 before RST high
Setup time, FS0/SD before CLKA↑
6
12
7
13
5
8
14
6
ns
ns
ns
ns
ns
su(RS)
su(FS)
su(SD)
‡
3.5
3.5
0.5
‡
Setup time, FS1/SEN before CLKA↑
5
6
su(SEN)
h(D)
Hold time, A0–A35 after CLKA↑ and B0–B35 after CLKB↑
0.5
0.5
Hold time, CSA, W/RA, ENA, and MBA after CLKA↑;
CSB, W/RB, ENB, RFM, and MBB after CLKB↑
t
0.5
0.5
0.5
ns
h(EN)
†
t
t
t
t
t
t
t
Hold time, RST low after CLKA↑ or CLKB↑
Hold time, FS0 and FS1 after RST high
Hold time, FS1/SEN high after RST high
Hold time, FS0/SD after CLKA↑
3.5
0.5
0.5
0.5
0
5
0.5
0.5
0.5
0
6
0.5
0.5
0.5
0
ns
ns
ns
ns
ns
ns
ns
h(RS)
h(FS)
‡
h(SP)
‡
h(SD)
‡
Hold time, FS1/SEN after CLKA↑
h(SEN)
§
Skew time between CLKA↑ and CLKB↑ for OR and IR
Skew time between CLKA↑ and CLKB↑ for AE and AF
7
9
11
sk(1)
§
8
12
16
sk(2)
†
‡
§
Requirement to count the clock edge as one of at least four needed to reset a FIFO
Applies only when serial load method is used to program flag offset registers
Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and
CLKB cycle.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 30 pF (see Figures 1 through 16)
L
’ALVC3631-10 ’ALVC3631-15 ’ALVC3631-20
’ALVC3641-10 ’ALVC3641-15 ’ALVC3641-20
’ALVC3651-10 ’ALVC3651-15 ’ALVC3651-20
PARAMETER
UNIT
MIN
100
2
MAX
MIN
MAX
MIN
50
2
MAX
f
t
t
t
t
t
66.7
MHz
ns
max
Access time, CLKB↑ to B0–B35
7.5
6.5
6.5
8
2
1
1
1
1
9.5
8
11.5
10
a
Propagation delay time, CLKA↑ to IR
Propagation delay time, CLKB↑ to OR
Propagation delay time, CLKB↑ to AE
Propagation delay time, CLKA↑ to AF
1
1
ns
pd(C-IR)
pd(C-OR)
pd(C-AE)
pd(C-AF)
1
8
1
10
ns
1
8
1
10
ns
1
8
8
1
10
ns
Propagation delay time, CLKA↑ to MBF1 low or MBF2 high
and CLKB↑ to MBF2 low or MBF1 high
t
t
0
2
6.5
11
0
2
8
0
2
10
13
ns
ns
pd(C-MF)
pd(C-MR)
Propagation delay time,
12
†
‡
CLKA↑ to B0–B35 and CLKB↑ to A0–A35
t
t
Propagation delay time, MBB to B0–B35 valid
2
1
9
2
1
10
2
1
12
ns
ns
pd(M-DV)
Propagation delay time, RST low to AE low and AF high
6.5
7.5
8.5
pd(R-F)
Enable time, CSA and W/RA low to A0–A35 active and CSB
low and W/RB high to B0–B35 active
t
en
2
10
2
11
2
12
ns
Disable time, CSA or W/RA high to A0–A35 at high
impedance and CSB high or W/RB low to B0–B35 at high
impedance
t
1
10
1
11
1
12
ns
dis
†
‡
Writing data to the mail1 register when the B0–B35 outputs are active and MBB is high
Writing data to the mail2 register when the A0–A35 outputs are active and MBA is high
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION
3.3 V
330 Ω
From Output
Under Test
30 pF
(see Note A)
510 Ω
LOAD CIRCUIT
3 V
3 V
High-Level
1.5 V
1.5 V
1.5 V
1.5 V
Timing
Input
Input
1.5 V
GND
GND
3 V
t
w
t
t
h
su
3 V
Data,
Enable
Input
Low-Level
Input
1.5 V
1.5 V
GND
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
GND
t
t
t
PLZ
PHZ
PZL
≈3 V
3 V
Low-Level
Output
1.5 V
1.5 V
1.5 V
Input
GND
V
OL
OH
t
t
pd
pd
t
PZH
V
V
OH
V
In-Phase
Output
High-Level
Output
1.5 V
1.5 V
1.5 V
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. Includes probe and jig capacitance
B.
C.
t
t
and t
and t
are the same as t
are the same as t
.
en
dis
PZL
PLZ
PZH
PHZ
.
Figure 16. Load Circuit and Voltage Waveforms
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC3631, SN74ALVC3641, SN74ALVC3651
512 × 36, 1024 × 36, 2048 × 36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SDMS025B – OCTOBER 1999 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
250
200
150
100
50
V
CC
V
CC
V
CC
= 3.6 V
= 3.3 V
= 3.0 V
f
T
C
= 1/2 f
clock
data
= 25°C
A
= 0 pF
L
0
0
20
40
60
80
100
f
– Clock Frequency – MHz
clock
Figure 17
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MBQF001A – NOVEMBER 1995
PQ (S-PQFP-G***)
PLASTIC QUAD FLATPACK
100 LEAD SHOWN
13
1 100
89
14
88
0.012 (0,30)
0.008 (0,20)
0.006 (0,15)
M
”D3” SQ
0.025 (0,635)
0.006 (0,16) NOM
64
38
0.150 (3,81)
0.130 (3,30)
39
63
Gage Plane
”D1” SQ
”D” SQ
0.010 (0,25)
0.020 (0,51) MIN
Seating Plane
”D2” SQ
0°–8°
0.046 (1,17)
0.036 (0,91)
0.004 (0,10)
0.180 (4,57) MAX
LEADS ***
100
132
DIM
MAX
MIN
0.890 (22,61)
0.870 (22,10)
0.766 (19,46)
0.734 (18,64)
0.912 (23,16)
0.888 (22,56)
0.600 (15,24)
1.090 (27,69)
1.070 (27,18)
0.966 (24,54)
0.934 (23,72)
1.112 (28,25)
1.088 (27,64)
0.800 (20,32)
”D”
MAX
MIN
”D1”
MAX
MIN
”D2”
”D3”
NOM
4040045/C 11/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-069
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MHTQ004A – JANUARY 1995 – REVISED JANUARY 1998
PCB (S-PQFP-G120)
PLASTIC QUAD FLATPACK (DIE DOWN)
0,23
0,13
M
0,07
0,40
90
61
Heat Slug
60
91
31
120
0,13 NOM
1
30
11,60 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040202/C 12/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Thermally enhanced molded plastic package with a heat slug (HSL)
D. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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