SN74ALVCH162344DGVR [TI]

ALVC/VCX/A SERIES, QUAD 2-BIT DRIVER, TRUE OUTPUT, PDSO56, TVSOP-56;
SN74ALVCH162344DGVR
型号: SN74ALVCH162344DGVR
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

ALVC/VCX/A SERIES, QUAD 2-BIT DRIVER, TRUE OUTPUT, PDSO56, TVSOP-56

驱动 光电二极管 输出元件 逻辑集成电路 电视
文件: 总14页 (文件大小:329K)
中文:  中文翻译
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SN74ALVCH162344  
1-BIT TO 4-BIT ADDRESS DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES085IAUGUST 1996REVISED OCTOBER 2004  
FEATURES  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments Widebus™  
Family  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OE1  
1B1  
1B2  
GND  
1B3  
1B4  
OE4  
8B1  
8B2  
GND  
8B3  
8B4  
Operates From 1.65 V to 3.6 V  
Max tpd of 4.4 ns at 3.3 V  
2
3
±12-mA Output Drive at 3.3 V  
4
Output Ports Have Equivalent 26-Series  
Resistors, So No External Resistors Are  
Required  
5
6
7
V
CC  
V
CC  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
8
1A  
2B1  
2B2  
GND  
2B3  
2B4  
2A  
8A  
9
7B1  
7B2  
GND  
7B3  
7B4  
7A  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
DESCRIPTION/ORDERING INFORMATION  
This 1-bit to 4-bit address driver is designed for  
1.65-V to 3.6-V VCC operation.  
3A  
6A  
3B1  
3B2  
GND  
3B3  
3B4  
4A  
6B1  
6B2  
GND  
6B3  
6B4  
5A  
The SN74ALVCH162344 is used in applications in  
which four separate memory locations must be  
addressed by a single address.  
The outputs, which are designed to sink up to 12 mA,  
include equivalent 26-resistors to reduce overshoot  
and undershoot.  
V
CC  
V
CC  
4B1  
4B2  
5B1  
5B2  
GND  
5B3  
5B4  
OE3  
To ensure the high-impedance state during power up  
or power down, the output-enable (OE) inputs should  
be tied to VCC through a pullup resistor; the minimum  
value of the resistor is determined by the  
current-sinking capability of the driver.  
GND  
4B3  
4B4  
OE2  
Active bus-hold circuitry holds unused or undriven  
inputs at a valid logic state. Use of pullup or pulldown  
resistors with the bus-hold circuitry is not  
recommended.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74ALVCH162344DL  
TOP-SIDE MARKING  
Tube  
SSOP - DL  
ALVCH162344  
Tape and reel  
SN74ALVCH162344DLR  
SN74ALVCH162344GR  
-40°C to 85°C  
TSSOP - DGG  
TVSOP - DGV  
Tape and reel  
Tape and reel  
ALVCH162344  
VH2344  
SN74ALVCH162344VR  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1996–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
SN74ALVCH162344  
1-BIT TO 4-BIT ADDRESS DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES085IAUGUST 1996REVISED OCTOBER 2004  
A-TO-B FUNCTION TABLE  
INPUTS  
OUTPUT  
Bn  
OE  
L
A
H
L
H
L
L
H
X
Z
2
SN74ALVCH162344  
1-BIT TO 4-BIT ADDRESS DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES085IAUGUST 1996REVISED OCTOBER 2004  
LOGIC DIAGRAM (POSITIVE LOGIC)  
56  
OE4  
29  
28  
OE3  
OE2  
OE1  
1
8
2
3
34  
33  
31  
30  
41  
40  
38  
37  
48  
47  
45  
44  
55  
54  
52  
51  
1B1  
1B2  
1B3  
5B1  
5B2  
5B3  
36  
42  
43  
49  
1A  
2A  
3A  
4A  
5A  
6A  
7A  
8A  
5
6
1B4  
2B1  
2B2  
2B3  
2B4  
3B1  
3B2  
3B3  
3B4  
4B1  
4B2  
4B3  
4B4  
5B4  
6B1  
6B2  
6B3  
6B4  
7B1  
7B2  
7B3  
7B4  
8B1  
8B2  
8B3  
8B4  
9
10  
12  
13  
16  
17  
19  
20  
23  
24  
26  
27  
14  
15  
21  
3
SN74ALVCH162344  
1-BIT TO 4-BIT ADDRESS DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES085IAUGUST 1996REVISED OCTOBER 2004  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
-0.5  
-0.5  
-0.5  
MAX  
4.6  
UNIT  
VCC  
VI  
Supply voltage range  
Input voltage range(2)  
Output voltage range(2)(3)  
V
4.6  
VCC + 0.5  
-50  
V
VO  
IIK  
V
Input clamp current  
VI < 0  
mA  
mA  
mA  
mA  
IOK  
IO  
Output clamp current  
VO < 0  
-50  
Continuous output current  
Continuous current through each VCC or GND  
±50  
±100  
64  
DGG package  
DGV package  
DL package  
θJA  
Package thermal impedance(4)  
48  
°C/W  
56  
Tstg  
Storage temperature range  
-65  
150  
°C  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.  
(3) This value is limited to 4.6 V maximum.  
(4) The package thermal impedance is calculated in accordance with JESD 51-7.  
RECOMMENDED OPERATING CONDITIONS(1)  
MIN  
MAX  
UNIT  
VCC  
Supply voltage  
1.65  
3.6  
V
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
0.65 × VCC  
VIH  
High-level input voltage  
1.7  
2
V
V
0.35 × VCC  
VIL  
Low-level input voltage  
0.7  
0.8  
VCC  
VCC  
-2  
VI  
Input voltage  
0
0
V
V
VO  
Output voltage  
VCC = 1.65 V  
VCC = 2.3 V  
VCC = 2.7 V  
VCC = 3 V  
-6  
IOH  
High-level output current  
Low-level output current  
mA  
mA  
-8  
-12  
2
VCC = 1.65 V  
VCC = 2.3 V  
VCC = 2.7 V  
VCC = 3 V  
6
IOL  
8
12  
10  
85  
t/v  
Input transition rise or fall rate  
Operating free-air temperature  
ns/V  
TA  
-40  
°C  
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
4
SN74ALVCH162344  
1-BIT TO 4-BIT ADDRESS DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES085IAUGUST 1996REVISED OCTOBER 2004  
ELECTRICAL CHARACTERISTICS  
over recommended operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
1.65 V to 3.6 V  
1.65 V  
2.3 V  
MIN  
TYP(1)  
MAX UNIT  
IOH = -100 µA  
IOH = -2 mA  
IOH = -4 mA  
VCC - 0.2  
1.2  
1.9  
1.7  
2.4  
2
VOH  
2.3 V  
V
IOH = -6 mA  
3 V  
IOH = -8 mA  
IOH = -12 mA  
IOL = 100 µA  
IOL = 2 mA  
IOL = 4 mA  
2.7 V  
3 V  
2
1.65 V to 3.6 V  
1.65 V  
2.3 V  
0.2  
0.45  
0.4  
VOL  
2.3 V  
0.55  
0.55  
0.6  
V
IOL = 6 mA  
3 V  
IOL = 8 mA  
2.7 V  
IOL = 12 mA  
VI = VCC or GND  
VI = 0.58 V  
VI = 1.07 V  
VI = 0.7 V  
3 V  
0.8  
II  
3.6 V  
±5  
µA  
µA  
1.65 V  
1.65 V  
2.3 V  
25  
-25  
45  
II(hold)  
VI = 1.7 V  
2.3 V  
-45  
75  
VI = 0.8 V  
3 V  
VI = 2 V  
3 V  
-75  
VI = 0 to 3.6 V(2)  
3.6 V  
±500  
±10  
40  
IOZ  
VO = VCC or GND  
3.6 V  
µA  
µA  
µA  
ICC  
VI = VCC or GND, IO = 0  
3.6 V  
ICC  
One input at VCC - 0.6 V, Other inputs at VCC or GND  
3 V to 3.6 V  
750  
Control inputs  
Data inputs  
Outputs  
2.5  
3.5  
4
Ci  
VI = VCC or GND  
VO = VCC or GND  
3.3 V  
3.3 V  
pF  
pF  
Co  
(1) All typical values are at VCC = 3.3 V, TA = 25°C.  
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to  
another.  
SWITCHING CHARACTERISTICS  
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)  
VCC = 2.5 V  
± 0.2 V  
VCC = 3.3 V  
± 0.3 V  
VCC = 1.8 V  
VCC = 2.7 V  
MIN MAX  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
TYP  
MIN  
1
MAX  
MIN  
1.4  
1.2  
1.2  
MAX  
(1)  
tpd  
ten  
tdis  
A
B
B
B
4.9  
6.4  
5.4  
5.1  
6.6  
4.7  
4.4  
5.7  
ns  
ns  
ns  
ns  
ns  
(1)  
(1)  
OE  
OE  
1
1
4.5  
(2)  
tsk(o)  
0.35  
0.5  
(3)  
tsk(o)  
(1) This information was not available at the time of publication.  
(2) Skew between outputs of the same bank and same package (same transition)  
(3) Skew between outputs of all banks of same package (A1–A8 tied together)  
5
SN74ALVCH162344  
1-BIT TO 4-BIT ADDRESS DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES085IAUGUST 1996REVISED OCTOBER 2004  
OPERATING CHARACTERISTICS  
TA = 25°C  
VCC = 1.8 V  
VCC = 2.5 V  
VCC = 3.3 V  
PARAMETER  
TEST CONDITIONS  
UNIT  
TYP  
TYP  
68  
TYP  
82  
(1)  
Outputs enabled  
Outputs disabled  
Power dissipation  
capacitance  
Cpd  
CL = 0 pF, f = 10 MHz  
pF  
(1)  
12  
14  
(1) This information was not available at the time of publication.  
6
SN74ALVCH162344  
1-BIT TO 4-BIT ADDRESS DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES085IAUGUST 1996REVISED OCTOBER 2004  
PARAMETER MEASUREMENT INFORMATION  
V
LOAD  
S1  
Open  
R
L
From Output  
Under Test  
TEST  
S1  
GND  
t
Open  
V
LOAD  
GND  
pd  
/t  
/t  
C
t
t
L
PLZ PZL  
R
L
(see Note A)  
PHZ PZH  
LOAD CIRCUIT  
INPUT  
V
CC  
V
M
V
LOAD  
C
L
R
L
V
V
I
t /t  
r f  
1.8 V ± 0.15 V  
2.5 V ± 0.2 V  
2.7 V  
V
V
2.7 V  
2.7 V  
V
/2  
/2  
2 × V  
2 × V  
6 V  
6 V  
1 k  
500 Ω  
500 Ω  
500 Ω  
0.15 V  
0.15 V  
0.3 V  
2 ns  
2 ns  
2.5 ns  
2.5 ns  
30 pF  
30 pF  
50 pF  
50 pF  
CC  
CC  
CC  
V
CC  
CC  
CC  
1.5 V  
1.5 V  
3.3 V ± 0.3 V  
0.3 V  
t
w
V
I
V
I
V
M
V
M
Input  
Timing  
Input  
V
M
0 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
t
su  
t
h
V
I
Output  
Control  
(low-level  
enabling)  
Data  
Input  
V
I
V
V
M
M
V
M
V
M
0 V  
0 V  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
t
t
PLZ  
PZL  
Output  
Waveform 1  
S1 at V  
LOAD  
(see Note B)  
V
V
/2  
LOAD  
V
I
V
M
Input  
V
M
V
M
V + V  
OL  
0 V  
OL  
t
t
PZH  
PHZ  
t
t
PHL  
PLH  
Output  
Waveform 2  
S1 at GND  
V
OH  
V
V
OH  
V
OH  
− V  
V
M
Output  
V
M
V
M
0 V  
OL  
(see Note B)  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 .  
O
D. The outputs are measured one at a time, with one transition per measurement.  
E.  
F.  
G.  
t
t
t
and t  
and t  
and t  
are the same as t  
.
dis  
.
PLZ  
PZL  
PLH  
PHZ  
are the same as t  
PZH  
en  
are the same as t .  
PHL pd  
H. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
7
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Nov-2009  
PACKAGING INFORMATION  
Orderable Device  
74ALVCH162344DLG4  
74ALVCH162344GRE4  
74ALVCH162344GRG4  
74ALVCH162344VRE4  
74ALVCH162344VRG4  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SSOP  
DL  
56  
56  
56  
56  
56  
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
TSSOP  
TVSOP  
TVSOP  
DGG  
DGG  
DGV  
DGV  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74ALVCH162344DGGR OBSOLETE TSSOP  
DGG  
DL  
56  
56  
TBD  
Call TI  
Call TI  
SN74ALVCH162344DL  
SN74ALVCH162344GR  
SN74ALVCH162344VR  
ACTIVE  
ACTIVE  
ACTIVE  
SSOP  
TSSOP  
TVSOP  
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
DGG  
DGV  
56  
56  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
29-Jul-2009  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
SN74ALVCH162344GR TSSOP  
SN74ALVCH162344VR TVSOP  
DGG  
DGV  
56  
56  
2000  
2000  
330.0  
330.0  
24.4  
24.4  
8.6  
6.8  
15.6  
11.7  
1.8  
1.6  
12.0  
12.0  
24.0  
24.0  
Q1  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
29-Jul-2009  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
SN74ALVCH162344GR  
SN74ALVCH162344VR  
TSSOP  
TVSOP  
DGG  
DGV  
56  
56  
2000  
2000  
346.0  
346.0  
346.0  
346.0  
41.0  
41.0  
Pack Materials-Page 2  
MECHANICAL DATA  
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001  
DL (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
48 PINS SHOWN  
0.025 (0,635)  
48  
0.0135 (0,343)  
0.008 (0,203)  
0.005 (0,13)  
M
25  
0.010 (0,25)  
0.005 (0,13)  
0.299 (7,59)  
0.291 (7,39)  
0.420 (10,67)  
0.395 (10,03)  
Gage Plane  
0.010 (0,25)  
0°ā8°  
1
24  
0.040 (1,02)  
0.020 (0,51)  
A
Seating Plane  
0.004 (0,10)  
0.008 (0,20) MIN  
PINS **  
0.110 (2,79) MAX  
28  
48  
0.630  
56  
DIM  
0.380  
(9,65)  
0.730  
A MAX  
A MIN  
(16,00) (18,54)  
0.370  
(9,40)  
0.620  
0.720  
(15,75) (18,29)  
4040048/E 12/01  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).  
D. Falls within JEDEC MO-118  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998  
DGG (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
48 PINS SHOWN  
0,27  
0,17  
M
0,08  
0,50  
48  
25  
6,20  
6,00  
8,30  
7,90  
0,15 NOM  
Gage Plane  
0,25  
1
24  
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
48  
56  
64  
DIM  
A MAX  
12,60  
12,40  
14,10  
13,90  
17,10  
16,90  
A MIN  
4040078/F 12/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000  
DGV (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
24 PINS SHOWN  
0,23  
0,13  
M
0,07  
0,40  
24  
13  
0,16 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
0°ā8°  
0,75  
1
12  
0,50  
A
Seating Plane  
0,08  
0,15  
0,05  
1,20 MAX  
PINS **  
14  
16  
20  
24  
38  
48  
56  
DIM  
A MAX  
A MIN  
3,70  
3,50  
3,70  
3,50  
5,10  
4,90  
5,10  
4,90  
7,90  
7,70  
9,80  
9,60  
11,40  
11,20  
4073251/E 08/00  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.  
D. Falls within JEDEC: 24/48 Pins – MO-153  
14/16/20/56 Pins – MO-194  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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