SN74ALVCH16260DGGR [TI]
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS;
| 型号： | SN74ALVCH16260DGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总10页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES046E – JULY 1995 – REVISED FEBRUARY 1999
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
OEA
LE1B
2B3
GND
2B2
OE2B
LEA2B
2B4
GND
2B5
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
3
4
5
Latch-Up Performance Exceeds 250 mA Per
JESD 17
2B1
2B6
6
V
V
7
CC
CC
A1
A2
A3
GND
A4
A5
A6
A7
A8
2B7
2B8
2B9
8
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 12-bit to 24-bit multiplexed D-type latch is
designed for 1.65-V to 3.6-V operation.
A9
CC
GND
A10
A11
A12
The SN74ALVCH16260 is used in applications in
which two separate data paths must be
multiplexed onto, or demultiplexed from, a single
data path. Typical applications include
multiplexing and/or demultiplexing address and
1B8
1B7
V
V
CC
CC
1B1
1B2
GND
1B3
LE2B
SEL
1B6
1B5
GND
1B4
LEA1B
OE1B
data
information
in
microprocessor
or
bus-interface applications. This device also is
useful in memory-interleaving applications.
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and
2B1–2B12) are available for address and/or data
transfer. The output-enable (OE1B, OE2B, and
OEA) inputs control the bus transceiver functions.
The OE1B and OE2B control signals also allow
bank control in the A-to-B direction.
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B,
LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the
latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains
latched until the latch-enable input is returned high.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16260 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES046E – JULY 1995 – REVISED FEBRUARY 1999
Function Tables
B TO A (OEB = H)
INPUTS
OUTPUT
A
1B
H
L
2B
X
SEL LE1B LE2B OEA
H
H
H
L
H
H
L
X
X
X
H
H
L
L
L
L
L
L
L
H
H
L
X
X
X
A
0
X
H
L
X
X
X
X
H
X
L
L
X
X
L
A
0
X
X
X
X
Z
A TO B (OEA = H)
INPUTS
LEA1B LEA2B OE1B OE2B
OUTPUTS
A
H
L
1B
2B
H
H
H
H
H
L
H
H
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
L
L
H
L
L
H
L
H
L
2B
2B
H
0
L
0
H
L
H
H
L
1B
0
1B
0
1B
0
Z
L
L
X
X
X
X
X
L
2B
Z
0
X
X
X
X
X
X
X
X
Active
Z
Z
Active
Active
Active
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES046E – JULY 1995 – REVISED FEBRUARY 1999
logic diagram (positive logic)
2
LE1B
27
LE2B
30
LEA1B
55
LEA2B
56
OE2B
29
OE1B
1
OEA
28
SEL
G1
C1
1D
8
23
A1
1B1
1
1
C1
6
2B1
1D
C1
1D
C1
1D
To 11 Other Channels
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES046E – JULY 1995 – REVISED FEBRUARY 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V : Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
CC
CC
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN
1.65
MAX
UNIT
V
Supply voltage
3.6
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
0.65 × V
1.7
CC
V
High-level input voltage
V
V
2
0.35 × V
0.7
CC
V
IL
Low-level input voltage
0.8
V
V
Input voltage
0
0
V
V
V
V
I
CC
Output voltage
O
CC
–4
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
–12
–12
–24
4
I
High-level output current
Low-level output current
mA
mA
OH
OL
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
12
I
12
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
T
A
–40
85
°C
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES046E – JULY 1995 – REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
–0.2
MAX
UNIT
V
CC
I
I
I
= –100 µA
= –4 mA
= –6 mA
1.65 V to 3.6 V
1.65 V
2.3 V
V
OH
OH
OH
CC
1.2
2
V
OH
2.3 V
1.7
2.2
2.4
2
V
I
= –12 mA
2.7 V
OH
3 V
I
I
I
I
= –24 mA
= 100 µA
= 4 mA
3 V
OH
OL
OL
OL
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
= 6 mA
V
OL
V
2.3 V
0.7
I
= 12 mA
OL
2.7 V
0.4
I
= 24 mA
3 V
0.55
±5
OL
I
I
V = V
or GND
3.6 V
µA
I
CC
V = 0.58 V
1.65 V
1.65 V
2.3 V
25
–25
45
I
V = 1.07 V
I
V = 0.7 V
I
I
V = 1.7 V
2.3 V
–45
75
µA
I(hold)
I
V = 0.8 V
I
3 V
V = 2 V
I
3 V
–75
‡
V = 0 to 3.6 V
3.6 V
±500
±10
40
I
§
I
I
V
O
= V
or GND
CC
or GND,
3.6 V
µA
µA
µA
pF
pF
OZ
V = V
I
I = 0
O
3.6 V
CC
CC
∆I
CC
One input at V
– 0.6 V,
Other inputs at V
CC
or GND
3 V to 3.6 V
3.3 V
750
CC
or GND
C
C
Control inputs V = V
3.5
9
i
I
CC
= V
A or B ports
V
or GND
3.3 V
io
O
CC
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
CC
A
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
For I/O ports, the parameter I
OZ
includes the input leakage current.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
V
= 2.5 V
V
= 3.3 V
CC
± 0.2 V
CC
± 0.3 V
V
= 1.8 V
MAX
V
= 2.7 V
MAX
CC
CC
UNIT
MIN
MIN
MAX
MIN
MIN
MAX
¶
t
w
t
su
t
h
Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high
3.3
3.3
3.3
ns
ns
ns
Setup time, data before LE1B, LE2B, LEA1B, or
LEA2B
¶
¶
1.4
1.6
1.1
1.9
1.1
1.5
Hold time, data after LE1B, LE2B, LEA1B, or LEA2B
¶
This information was not available at the time of publication.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES046E – JULY 1995 – REVISED FEBRUARY 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
V
= 2.5 V
V
= 3.3 V
CC
± 0.2 V
CC
± 0.3 V
V
CC
= 1.8 V
V
= 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
TYP
MIN
1
MAX
5.4
5.6
6.9
6.7
5.7
MIN
MAX
5.1
5.2
6.6
6.4
5
MIN
1.2
1
MAX
4.3
4.4
5.6
5.4
4.6
†
†
†
†
†
A or B
LE
B or A
A or B
A
t
pd
1
ns
SEL
OE
1
1.1
1
t
t
A or B
A or B
1
ns
ns
en
1
1.3
OE
dis
†
This information was not available at the time of publication.
operating characteristics, T = 25°C
A
V
= 1.8 V
CC
TYP
V
= 2.5 V
CC
TYP
V = 3.3 V
CC
PARAMETER
TEST CONDITIONS
UNIT
TYP
†
†
All outputs enabled
All outputs disabled
37
4
41
7
Power dissipation
capacitance
C
C
= 50 pF,
L
f = 10 MHz
pF
pd
†
This information was not available at the time of publication.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES046E – JULY 1995 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
= 1.8 V
V
CC
2 × V
CC
Open
S1
1 kΩ
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
1 kΩ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES046E – JULY 1995 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES046E – JULY 1995 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
6 V
Open
GND
S1
TEST
S1
500 Ω
From Output
Under Test
t
pd
Open
6 V
t
/t
PLZ PZL
C
= 50 pF
L
t
/t
GND
500 Ω
PHZ PZH
(see Note A)
t
w
LOAD CIRCUIT
2.7 V
0 V
1.5 V
1.5 V
Input
2.7 V
Timing
Input
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
2.7 V
0 V
Data
Input
Output
1.5 V
1.5 V
2.7 V
0 V
Control
(low-level
enabling)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
3 V
2.7 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
+ 0.3 V
OL
V
(see Note B)
OL
OH
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
V
OH
– 0.3 V
1.5 V
Output
1.5 V
1.5 V
0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 3. Load Circuit and Voltage Waveforms
9
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