SN74ALVCH162827DGV [TI]
20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS; 20位缓冲器/驱动器，具有三态输出
| 型号： | SN74ALVCH162827DGV |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS |
| 文件： | 总10页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALVCH162827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES013H–JULY 1995–REVISED AUGUST 2004
FEATURES
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
•
Member of the Texas Instruments Widebus™
Family
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE1
1Y1
1Y2
GND
1Y3
1OE2
1A1
1A2
GND
1A3
•
Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
2
3
4
•
•
•
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
5
6
1Y4
1A4
Latch-Up Performance Exceeds 250 mA Per
JESD 17
7
V
CC
V
CC
8
1Y
1Y6
1Y7
GND
1Y8
1Y9
1Y10
2Y1
2Y2
2Y3
GND
2Y4
2Y5
2Y6
1A5
1A6
1A7
GND
1A8
1A9
1A10
2A1
2A2
2A3
GND
2A4
2A5
2A6
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
- 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 20-bit noninverting buffer/driver is designed for
1.65-V to 3.6-V VCC operation.
The SN74ALVCH162827 is composed of two 10-bit
sections with separate output-enable signals. For
either 10-bit buffer section, the two output-enable
(1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must
both be low for the corresponding Y outputs to be
active. If either output-enable input is high, the
outputs of that 10-bit buffer section are in the
high-impedance state.
V
CC
V
CC
2Y7
2Y8
GND
2Y9
2Y10
2OE1
2A7
2A8
GND
2A9
2A10
2OE2
The outputs, which are designed to sink up to 12 mA,
include equivalent 26-Ω resistors to reduce overshoot
and undershoot.
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74ALVCH162827DL
TOP-SIDE MARKING
Tube
SSOP - DL
ALVCH162827
Tape and reel
SN74ALVCH162827DLR
SN74ALVCH162827GR
-40°C to 85°C
TSSOP - DGG
TVSOP - DGV
Tape and reel
Tape and reel
ALVCH162827
VH2827
SN74ALVCH162827VR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74ALVCH162827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES013H–JULY 1995–REVISED AUGUST 2004
FUNCTION TABLE
(each 10-bit section)
INPUTS
OUTPUT
Y
OE1
L
OE2
L
A
L
L
H
Z
Z
L
L
H
X
X
H
X
X
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1
28
1OE1
2OE1
56
29
1OE2
2OE2
55
2
42
15
1A1
1Y1
2A1
2Y1
To Nine Other Channels
To Nine Other Channels
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
-0.5
-0.5
MAX
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Output voltage range(2)(3)
Input clamp current
4.6
4.6
V
VO
IIK
-0.5 VCC + 0.5
V
VI < 0
-50
-50
±50
±100
64
mA
mA
mA
mA
IOK
IO
Output clamp current
Continuous output current
VO < 0
Continuous current through each VCC or GND
DGG package
DGV package
DL package
θJA
Package thermal impedance(4)
48
°C/W
56
Tstg
Storage temperature range
-65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2
SN74ALVCH162827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES013H–JULY 1995–REVISED AUGUST 2004
RECOMMENDED OPERATING CONDITIONS(1)
MIN
MAX
UNIT
VCC
Supply voltage
1.65
3.6
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
V
0.35 × VCC
VIL
Low-level input voltage
0.7
0.8
VCC
VCC
-2
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
-6
IOH
High-level output current
Low-level output current
mA
mA
-8
-12
2
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
6
IOL
8
12
10
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
TA
-40
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
SN74ALVCH162827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES013H–JULY 1995–REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V VCC - 0.2
MIN TYP(1)
MAX
UNIT
IOH = -100 µA
IOH = -2 mA
IOH = -4 mA
1.65 V
2.3 V
1.2
1.9
1.7
2.4
2
VOH
2.3 V
V
IOH = -6 mA
3 V
IOH = -8 mA
IOH = -12 mA
IOL = 100 µA
IOL = 2 mA
IOL = 4 mA
2.7 V
3 V
2
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
VOL
2.3 V
0.55
0.55
0.6
V
IOL = 6 mA
3 V
IOL = 8 mA
2.7 V
IOL = 12 mA
VI = VCC or GND
VI = 0.58 V
3 V
0.8
II
3.6 V
±5
µA
µA
1.65 V
1.65 V
2.3 V
25
-25
45
VI = 1.07 V
VI = 0.7 V
II(hold)
VI = 1.7 V
2.3 V
-45
75
VI = 0.8 V
3 V
VI = 2 V
3 V
-75
VI = 0 to 3.6 V(2)
VO = VCC or GND
VI = VCC or GND,
3.6 V
±500
±10
40
IOZ
3.6 V
µA
µA
µA
ICC
IO = 0
3.6 V
∆ICC
One input at VCC - 0.6 V, Other inputs at VCC or GND
3 V to 3.6 V
750
Control inputs
Data inputs
Outputs
3.5
6
Ci
VI = VCC or GND
3.3 V
3.3 V
pF
pF
Co
VO = VCC or GND
7
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
4
SN74ALVCH162827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES013H–JULY 1995–REVISED AUGUST 2004
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.8 V
VCC = 2.7 V
MIN MAX
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
(1)
MIN
MAX
4.4
6.3
5.9
0.5
0.5
MIN
1.5
1.6
1.8
MAX
tpd
ten
tdis
A
Y
Y
Y
1
1.4
1.7
4.4
6.2
5.2
0.5
0.5
3.8
5.1
4.7
0.5
0.5
ns
ns
ns
(1)
(1)
(1)
(1)
OE
OE
(2)
tsk(LH)
A
Y
ns
(2)
tsk(HL)
(1) This information was not available at the time of publication.
(2) Parameter specified by design
tsk(LH) = |tPLH(m) - tPLH(n)|
tsk(HL) = |tPHL(m) - tPHL(n)|
where m and n are any arbitrary data bits.
OPERATING CHARACTERISTICS
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
16
4
TYP
18
6
(1)
Outputs enabled
Cpd
Power dissipation capacitance
CL = 50 pF, f = 10 MHz
pF
(1)
Outputs disabled
(1) This information was not available at the time of publication.
5
SN74ALVCH162827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES013H–JULY 1995–REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
S1
GND
t
Open
V
LOAD
GND
pd
/t
/t
C
t
t
L
PLZ PZL
R
L
(see Note A)
PHZ PZH
LOAD CIRCUIT
INPUT
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V
2.5 V ± 0.2 V
2.7 V
V
V
2.7 V
2.7 V
V
/2
/2
2 × V
2 × V
6 V
6 V
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
30 pF
30 pF
50 pF
50 pF
CC
CC
CC
V
CC
CC
CC
1.5 V
1.5 V
3 V ± 0.3 V
0.3 V
t
w
V
I
V
I
V
M
V
M
Input
Timing
Input
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
I
Output
Control
(low-level
enabling)
Data
Input
V
I
V
V
M
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at V
LOAD
(see Note B)
V
V
/2
LOAD
V
I
V
M
Input
V
M
V
M
V + V
∆
OL
0 V
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− V
∆
V
M
Output
V
M
V
M
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
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Copyright 2004, Texas Instruments Incorporated
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