SN74ALVCH162836GR [TI]
具有三态输出的 20 位通用总线驱动器 | DGG | 56 | -40 to 85;
| 型号： | SN74ALVCH162836GR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有三态输出的 20 位通用总线驱动器 | DGG | 56 | -40 to 85 驱动 光电二极管 逻辑集成电路 总线驱动器 总线收发器 |
| 文件： | 总10页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALVCH162836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES122E – JULY 1997 – REVISED JUNE 1999
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
OE
Y1
Y2
GND
Y3
Y4
1
2
3
4
5
6
7
8
9
10
56 CLK
55 A1
54 A2
53 GND
52 A3
51 A4
Output Port Has Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
Designed to Comply With JEDEC 168-Pin
and 200-Pin SDRAM Buffered DIMM
Specification
V
50
V
CC
Y5
CC
49 A5
48 A6
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Y6
Y7
GND 11
Y8 12
47
A7
46 GND
45 A8
Latch-Up Performance Exceeds 250 mA Per
JESD 17
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Y9
Y10
Y11
Y12
Y13
GND
Y14
Y15
Y16
A9
A10
A11
A12
A13
GND
A14
A15
A16
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
NOTE: For tape and reel order entry:
V
V
The DGGR package is abbreviated to GR, and
the DGVR package is abbreviated to VR.
CC
CC
Y17
Y18
GND
Y19
Y20
NC
A17
A18
GND
A19
A20
LE
description
This 20-bit universal bus driver is designed for
1.65-V to 3.6-V V
operation.
CC
Data flow from A to Y is controlled by the
output-enable (OE) input. The device operates in
the transparent mode when the latch-enable (LE)
input is low. When LE is high, the A data is latched
if the clock (CLK) input is held at a high or low logic
level. If LE is high, the A data is stored in the
latch/flip-flop on the low-to-high transition of CLK.
When OE is high, the outputs are in the
high-impedance state.
NC – No internal connection
The output port includes equivalent 26-Ω series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162836 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH162836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES122E – JULY 1997 – REVISED JUNE 1999
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE
LE
X
CLK
A
X
L
H
L
L
L
L
L
X
Z
L
L
X
L
X
H
L
H
L
H
H
H
↑
↑
H
X
H
†
Y
0
L or H
†
Output level before the indicated steady-state
input conditions were established
‡
logic symbol
1
EN1
OE
56
29
CLK
2C3
C3
LE
G2
2
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
Y1
Y2
1
1
3D
A1
3
A2
5
Y3
A3
6
Y4
A4
8
Y5
A5
9
Y6
A6
10
12
13
14
15
16
17
19
20
21
23
Y7
A7
Y8
A8
Y9
A9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
A10
A11
A12
A13
A14
A15
A16
Y17
Y18
Y19
Y20
A17
A18
A19
A20
24
26
27
33
31
30
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH162836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES122E – JULY 1997 – REVISED JUNE 1999
logic diagram (positive logic)
1
OE
56
CLK
29
LE
55
1D
C1
A1
2
Y1
CLK
To 19 Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH162836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES122E – JULY 1997 – REVISED JUNE 1999
recommended operating conditions (see Note 4)
MIN
1.65
MAX
UNIT
V
Supply voltage
3.6
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
0.65 × V
1.7
CC
V
High-level input voltage
V
V
2
0.35 × V
0.7
CC
V
IL
Low-level input voltage
0.8
V
V
Input voltage
0
0
V
V
V
V
I
CC
Output voltage
O
CC
–2
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
–6
–8
I
High-level output current
Low-level output current
mA
mA
OH
OL
–12
2
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
6
I
8
12
10
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
A
–40
°C
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH162836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES122E – JULY 1997 – REVISED JUNE 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
–0.2
MAX
UNIT
V
CC
I
I
I
= –100 µA
= –2 mA
= –4 mA
1.65 V to 3.6 V
1.65 V
2.3 V
V
OH
OH
OH
CC
1.2
1.9
1.7
2.4
2
V
OH
2.3 V
V
I
= –6 mA
OH
3 V
I
I
I
I
I
= –8 mA
= –12 mA
= 100 µA
= 2 mA
2.7 V
OH
OH
OL
OL
OL
3 V
2
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
= 4 mA
V
OL
2.3 V
0.55
0.55
0.6
V
I
= 6 mA
OL
3 V
I
I
= 8 mA
2.7 V
OL
= 12 mA
3 V
0.8
OL
I
V = V
or GND
3.6 V
±5
µA
µA
I
I
CC
V = 0.58 V
I
1.65 V
1.65 V
2.3 V
25
–25
45
V = 1.07 V
I
V = 0.7 V
I
I
V = 1.7 V
I
2.3 V
–45
75
I(hold)
V = 0.8 V
I
3 V
V = 2 V
I
3 V
–75
‡
V = 0 to 3.6 V
3.6 V
±500
±10
40
I
I
I
V
O
= V
or GND
CC
or GND,
3.6 V
µA
µA
µA
OZ
V = V
I
I = 0
O
3.6 V
CC
CC
∆I
CC
One input at V
– 0.6 V,
Other inputs at V
or GND
CC
3 V to 3.6 V
750
CC
Control inputs
Data inputs
Outputs
5.5
6
C
V = V or GND
CC
3.3 V
3.3 V
pF
pF
i
I
C
V
O
= V
or GND
8
o
CC
†
‡
All typical values are at V
= 3.3 V, T = 25°C.
CC
A
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH162836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES122E – JULY 1997 – REVISED JUNE 1999
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
V = 2.5 V
CC
± 0.2 V
V = 3.3 V
CC
± 0.3 V
V
CC
= 1.8 V
V
CC
= 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
†
f
t
Clock frequency
Pulse duration
150
150
150
MHz
ns
clock
†
†
†
†
†
†
LE low
3.3
3.3
1.4
1.2
1.4
0.9
3.3
3.3
1.7
1.6
1.5
0.9
3.3
3.3
1.5
1.3
1.2
0.9
w
CLK high or low
Data before CLK↑
t
Setup time
Hold time
CLK high
CLK low
ns
ns
su
h
Data before LE↑
Data after CLK↑
Data after LE↑
t
CLK
high or low
†
1.1
1.1
1.1
†
This information was not available at the time of publication.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
V
= 2.5 V
V
= 3.3 V
CC
± 0.2 V
CC
± 0.3 V
V
= 1.8 V
TYP
V
= 2.7 V
MAX
FROM
(INPUT)
TO
(OUTPUT)
CC
CC
PARAMETER
UNIT
MIN
MIN
150
1
MAX
MIN
MIN
150
1.2
1.4
1.1
1.2
1.7
MAX
†
f
150
MHz
max
pd
†
†
†
†
†
A
4.4
5.8
5.2
6.4
4.7
4.6
6.1
5.5
6.5
5.2
4
5.1
5
t
LE
Y
1.1
1
ns
CLK
OE
OE
t
t
Y
Y
1.1
1
5.5
5.1
ns
ns
en
dis
†
This information was not available at the time of publication.
operating characteristics, T = 25°C
A
V
= 1.8 V
V
= 2.5 V
V = 3.3 V
CC
CC
TYP
CC
TYP
PARAMETER
TEST CONDITIONS
UNIT
TYP
36
10.5
†
†
Outputs enabled
Outputs disabled
31.5
8
Power dissipation
capacitance
C
C
= 0,
L
f = 10 MHz
pF
pd
†
This information was not available at the time of publication.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH162836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES122E – JULY 1997 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
= 1.8 V
V
CC
2 × V
CC
Open
S1
1 kΩ
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
1 kΩ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH162836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES122E – JULY 1997 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH162836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES122E – JULY 1997 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
6 V
S1
TEST
S1
Open
500 Ω
From Output
Under Test
t
Open
6 V
pd
/t
GND
t
PLZ PZL
/t
C
= 50 pF
t
GND
L
PHZ PZH
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
2.7 V
0 V
1.5 V
1.5 V
Input
2.7 V
Timing
Input
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
2.7 V
Data
Input
1.5 V
1.5 V
2.7 V
0 V
Output
Control
(low-level
enabling)
0 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
3 V
2.7 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
(see Note B)
OL
OH
t
t
t
PHL
PHZ
PLH
PZH
Output
Waveform 2
S1 at GND
V
V
OH
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 3. Load Circuit and Voltage Waveforms
9
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IMPORTANT NOTICE
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