SN74ALVCH16373KR [TI]
16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS; 16位透明D类锁存器具有三态输出
| 型号： | SN74ALVCH16373KR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS |
| 文件： | 总7页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES020F – JULY 1995 – REVISED MAY 2002
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
1OE
1Q1
1Q2
GND
1Q3
1Q4
1LE
1D1
1D2
GND
1D3
1D4
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
V
V
CC
CC
1Q5
1Q6
1D5
1D6
description
GND 10
39 GND
1Q7
1Q8
1D7
1D8
11
12
38
37
This 16-bit transparent D-type latch is designed
for 1.65-V to 3.6-V V operation.
CC
2Q1 13
2Q2 14
GND 15
2Q3 16
2Q4 17
36 2D1
35 2D2
34 GND
33 2D3
32 2D4
The SN74ALVCH16373 is particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
This device can be used as two 8-bit latches or
one 16-bit latch. When the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the levels set up at the D inputs.
V
18
31
V
CC
CC
2Q5 19
2Q6 20
GND 21
2Q7 22
2Q8 23
2OE 24
30 2D5
29 2D6
28 GND
27 2D7
26 2D8
25 2LE
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not affect internal operations of the latch. Old data
can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Activebus-holdcircuitryholdsunusedorundriveninputsatavalidlogicstate. Useofpulluporpulldownresistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74ALVCH16373DL
SN74ALVCH16373DLR
SN74ALVCH16373DGGR
SN74ALVCH16373KR
SSOP – DL
ALVCH16373
Tape and reel
–40°C to 85°C
TSSOP – DGG Tape and reel
VFBGA – GQL Tape and reel
ALVCH16373
VH373
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES020F – JULY 1995 – REVISED MAY 2002
GQL PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
A
B
C
D
E
F
1OE
1Q2
1Q4
1Q6
1Q8
2Q1
2Q3
2Q5
2Q7
2OE
NC
NC
NC
NC
1LE
1D2
1D4
1D6
1D8
2D1
2D3
2D5
2D7
2LE
1Q1
1Q3
1Q5
1Q7
2Q2
2Q4
2Q6
2Q8
NC
GND
GND
1D1
1D3
1D5
1D7
2D2
2D4
2D6
2D8
NC
V
CC
V
CC
GND
GND
G
H
J
GND
GND
G
H
J
V
CC
V
CC
GND
NC
GND
NC
K
K
NC – No internal connection
FUNCTION TABLE
(each 8-bit section)
INPUTS
OUTPUT
Q
LE
H
H
L
D
H
L
OE
L
H
L
L
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)
1
24
25
2OE
1OE
48
2LE
2D1
1LE
C1
1D
C1
2
13
2Q1
1Q1
47
36
1D1
1D
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DGG and DL packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES020F – JULY 1995 – REVISED MAY 2002
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN
1.65
MAX
UNIT
V
Supply voltage
3.6
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
0.65 × V
1.7
CC
V
High-level input voltage
V
V
2
0.35 × V
0.7
CC
V
IL
Low-level input voltage
0.8
V
V
Input voltage
0
0
V
V
V
V
I
CC
Output voltage
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
–4
–12
–12
–24
4
I
High-level output current
Low-level output current
mA
mA
OH
OL
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
12
I
12
24
∆t/∆v Input transition rise or fall rate
Operating free-air temperature
NOTE 4: All unused control inputs of the device must be held at V
10
ns/V
T
A
–40
85
°C
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES020F – JULY 1995 – REVISED MAY 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
V –0.2
CC
MAX
UNIT
V
CC
I
I
I
= –100 µA
= –4 mA
= –6 mA
1.65 V to 3.6 V
1.65 V
2.3 V
OH
OH
OH
1.2
2
V
OH
2.3 V
1.7
2.2
2.4
2
V
I
= –12 mA
2.7 V
OH
3 V
I
I
I
I
= –24 mA
= 100 µA
= 4 mA
3 V
OH
OL
OL
OL
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
= 6 mA
V
OL
V
2.3 V
0.7
I
= 12 mA
OL
2.7 V
0.4
I
= 24 mA
3 V
0.55
±5
OL
I
I
V = V
or GND
3.6 V
µA
I
CC
V = 0.58 V
1.65 V
1.65 V
2.3 V
25
–25
45
I
V = 1.07 V
I
V = 0.7 V
I
I
V = 1.7 V
2.3 V
–45
75
µA
I(hold)
I
V = 0.8 V
I
3 V
V = 2 V
I
3 V
–75
‡
V = 0 to 3.6 V
3.6 V
±500
±10
40
I
I
I
V
O
= V
or GND
CC
or GND,
3.6 V
µA
µA
µA
OZ
V = V
I
I = 0
O
3.6 V
CC
CC
∆I
CC
One input at V
– 0.6 V, Other inputs at V
or GND
CC
3 V to 3.6 V
750
CC
Control inputs
Data inputs
Outputs
3
6
7
C
V = V
CC
or GND
3.3 V
3.3 V
pF
pF
i
I
C
V
O
= V
or GND
o
CC
†
‡
All typical values are at V
= 3.3 V, T = 25°C.
CC
A
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V
= 2.5 V
V
= 3.3 V
CC
± 0.2 V
CC
± 0.3 V
V
= 1.8 V
MAX
V
= 2.7 V
MAX
CC
CC
UNIT
MIN
MIN
3.3
1
MAX
MIN
3.3
1
MIN
3.3
1.1
1.4
MAX
§
t
w
t
su
t
h
Pulse duration, LE high or low
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
§
§
1.5
1.7
§
This information was not available at the time of publication.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES020F – JULY 1995 – REVISED MAY 2002
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 2.5 V
V
= 3.3 V
CC
± 0.2 V
CC
± 0.3 V
V
CC
= 1.8 V
V
= 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
TYP
MIN
1
MAX
4.5
4.9
6
MIN
MAX
4.3
MIN
1.1
1
MAX
3.6
†
†
†
†
D
t
pd
Q
ns
LE
OE
OE
1
4.6
3.9
t
t
Q
Q
1
5.7
1
4.7
ns
ns
en
1.2
5.1
4.5
1.4
4.1
dis
†
This information was not available at the time of publication.
operating characteristics, T = 25°C
A
V
= 1.8 V
CC
TYP
V
= 2.5 V
CC
TYP
V = 3.3 V
CC
PARAMETER
TEST CONDITIONS
UNIT
TYP
†
†
Outputs enabled
Outputs disabled
19
4
22
5
Power dissipation
capacitance
C
C
= 50 pF,
L
f = 10 MHz
pF
pd
†
This information was not available at the time of publication.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES020F – JULY 1995 – REVISED MAY 2002
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
/t
C
t
t
V
L
PLZ PZL
LOAD
GND
R
L
(see Note A)
PHZ PZH
LOAD CIRCUIT
INPUT
V
CC
V
M
V
C
R
V
∆
LOAD
L
L
V
I
t /t
r f
1.8 V
2.5 V ± 0.2 V
2.7 V
V
V
V
/2
/2
2 × V
2 × V
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
≤2 ns
≤2 ns
30 pF
30 pF
50 pF
50 pF
CC
CC
CC
V
CC
CC
CC
2.7 V
2.7 V
1.5 V
1.5 V
6 V
6 V
≤2.5 ns
≤2.5 ns
3 V ± 0.3 V
0.3 V
t
w
V
I
V
I
V
M
V
M
Input
Timing
Input
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
I
Output
Control
(low-level
enabling)
Data
Input
V
I
V
V
M
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
+ V
Output
Waveform 1
V
V
/2
LOAD
V
I
V
M
Input
V
M
V
M
S1 at V
(see Note B)
V
OL
LOAD
∆
0 V
OL
t
t
PZH
PHZ
– V
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
∆
V
M
Output
V
M
V
M
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Post Office Box 655303
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Copyright 2002, Texas Instruments Incorporated
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