SN74ALVCH16973DL [TI]
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH FOUR INDEPENDENT BUFFERS; 8位总线收发器和透明D型锁存器具有四个独立的缓冲区
| 型号： | SN74ALVCH16973DL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH FOUR INDEPENDENT BUFFERS |
| 文件： | 总13页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
www.ti.com
SCES435B–APRIL 2003–REVISED SEPTEMBER 2004
FEATURES
DGG, DGV, OR DL PACKAGE
•
•
•
•
Member of the Texas Instruments Widebus™
Family
(TOP VIEW)
1
48 DIR
47 B1
46
TOE
D1
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
2
3
Q1
A1
GND
Y1
Latch-Up Performance Exceeds 250 mA Per
JESD 17
4
45 GND
44 B2
5
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
6
43 Q2
A2
7
42
41
40
39
V
CC
V
CC
8
B3
Q3
GND
D2
A3
GND
Y2
A4
D3
– 1000-V Charged-Device Model (C101)
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DESCRIPTION/ORDERING INFORMATION
38 B4
37 Q4
36 B5
This device contains four independent noninverting
buffers and an 8-bit noninverting bus transceiver and
D-type latch, designed for 1.65-V to 3.6-V VCC
operation.
35
34
33
32
31
30
29
28
27
26
25
Q5
GND
B6
A5
GND
Y3
The SN74ALVCH16973 is particularly suitable for
demultiplexing an address/data bus into a dedicated
address bus and dedicated data bus. The device is
used where there is asynchronous bidirectional
communication between the A and B data bus, and
the address signals are latched and buffered on the
Q bus. The control-function implementation minimizes
external timing requirements.
Q6
A6
V
CC
V
CC
B7
Q7
GND
Q8
B8
D4
A7
GND
A8
Y4
LE
LOE
This device can be used as one 4-bit buffer, one 8-bit
transceiver, or one 8-bit latch. It allows data
transmission from the A bus to the B bus or from the
B bus to the A bus, depending on the logic level at
the direction-control (DIR) input. The transceiver
output-enable (TOE) input can be used to disable the
transceivers so that the A and B buses effectively are
isolated.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74ALVCH16973DL
TOP-SIDE MARKING
Tube
SSOP - DL
ALVCH16973
Tape and reel
SN74ALVCH16973DLR
SN74ALVCH16973DGGR
SN74ALVCH16973DGVR
-40°C to 85°C
TSSOP - DGG
TVSOP - DGV
Tape and reel
Tape and reel
ALVCH16973
VH973
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
www.ti.com
SCES435B–APRIL 2003–REVISED SEPTEMBER 2004
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
When the latch-enable (LE) input is high, the Q outputs follow the data (A) inputs. When LE is taken low, the Q
outputs are latched at the levels set up at the A inputs. The latch output-enable (LOE) input can be used to place
the nine Q outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the
high-impedance state, the Q outputs neither drive nor load the bus lines significantly. LOE does not affect
internal operations of the latch. Old data can be retained or new data can be entered while the Q outputs are in
the high-impedance state.
To ensure the high-impedance state during power up or power down, LOE and TOE should be tied to VCC
through pullup resistors; the minimum values of the resistors are determined by the current-sinking capability of
the drivers.
The four independent noninverting buffers perform the Boolean function Y = D and are independent of the state
of DIR, TOE, LE, and LOE.
The A and B I/Os and D inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data
inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
FUNCTION TABLES
INPUTS
OPERATION
TOE
DIR
L
L
L
B data to A bus
A data to B bus
H
A bus and B bus
isolation
H
X
INPUTS
OUTPUT
Q
LOE
LE
H
H
L
A
H
L
L
L
H
L
L
X
X
Q0
Z
H
X
INPUT
D
OUTPUT
Y
L
L
H
H
2
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
www.ti.com
SCES435B–APRIL 2003–REVISED SEPTEMBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
48
DIR
1
TOE
25
24
LOE
LE
One of Eight Channels
C1
46
Q1
1D
3
A1
47
B1
To Seven Other Channels
One of Four Channels
2
5
D1
Y1
3
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
www.ti.com
SCES435B–APRIL 2003–REVISED SEPTEMBER 2004
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
-0.5
-0.5
-0.5
-0.5
MAX
4.6
UNIT
VCC
VI
Supply voltage range
Input voltage range
V
Except I/O and D input ports(2)
I/O and D input ports(2)(3)
4.6
VCC + 0.5
VCC + 0.5
-50
V
VO
IIK
Output voltage range(2)(3)
Input clamp current
V
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
-50
Continuous output current
Continuous current through each VCC or GND
±50
±100
70
DGG package
DGV package
DL package
θJA
Package thermal impedance(4)
58
°C/W
63
Tstg
Storage temperature range
-65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS(1)
MIN
MAX
UNIT
VCC
Supply voltage
1.65
3.6
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0.35 × VCC
0.7
0.8
VCC
VCC
-4
VIL
Low-level input voltage
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
-12
-12
-24
4
IOH
High-level output current
Low-level output current
mA
mA
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
12
IOL
12
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
TA
-40
85
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
www.ti.com
SCES435B–APRIL 2003–REVISED SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
1.65 V
2.3 V
MIN TYP(1) MAX UNIT
VCC - 0.2
IOH = -100 µA
IOH = -4 mA
IOH = -6 mA
1.2
2
VOH
2.3 V
1.7
2.2
2.4
2
V
IOH = -12 mA
2.7 V
3 V
IOH = -24 mA
IOL = 100 µA
IOL = 4 mA
IOL = 6 mA
3 V
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
VOL
V
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
VI = VCC or GND
VI = 0.57 V
VI = 0.7 V
3 V
0.55
±5
II
3.6 V
µA
µA
1.65 V
2.3 V
25
45
(2)
IBHL
VI = 0.8 V
3 V
75
VI = 1.07 V
VI = 1.7 V
1.65 V
2.3 V
-25
(3)
IBHH
-45
µA
µA
µA
VI = 2 V
3 V
-75
1.95 V
2.7 V
200
300
500
-200
-300
-500
(4)
(5)
IBHLO
VI = 0 to VCC
VI = 0 to VCC
3.6 V
1.95 V
2.7 V
IBHHO
3.6 V
(6)
IOZ
VO = VCC or GND
3.6 V
±10
µA
µA
ICC
VI = VCC or GND, IO = 0
3.6 V
30
One input at VCC - 0.6 V,
Other inputs at VCC or GND
∆ICC
3 V to 3.6 V
3.3 V
750
µA
Control inputs
3
4
Ci
VI = VCC or GND
pF
D
A ports
B ports
Q
4.5
4.5
3
Cio
Co
VO = VCC or GND
VO = VCC or GND
3.3 V
3.3 V
pF
pF
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND
and then raising it to VIL max.
(3) The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN
to VCC and then lowering it to VIH min.
(4) An external driver must source at least IBHLO to switch this node from low to high.
(5) An external driver must sink at least IBHHO to switch this node from high to low.
(6) For I/O ports, the parameter IOZ includes the input leakage current.
5
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
www.ti.com
SCES435B–APRIL 2003–REVISED SEPTEMBER 2004
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.8 V
UNIT
MIN
2
MAX
MIN
2
MAX
MIN
MAX
tw
tsu
th
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
2
0.9
0.9
ns
ns
ns
0.9
0.9
0.9
0.9
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 1.8 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
2.2
2.2
2.8
2.2
2.9
3
MIN
0.5
0.5
0.5
0.5
0.7
0.7
0.7
0.5
0.5
0.5
MAX
MIN
0.5
0.5
0.5
0.5
0.7
0.7
0.7
0.5
0.5
0.5
MAX
D
A
Y
3.2
3.2
3.3
3.2
4.9
4.6
4.9
4.3
4.3
4.9
3
3
tpd
Q
ns
LE
3
A or B
LOE
TOE
DIR
LOE
TOE
DIR
B or A
Q
3
4.7
4.4
4.7
4.1
4.1
4.7
ten
ns
ns
A or B
Q
3.4
2.8
3.2
3.4
tdis
A or B
6
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
www.ti.com
SCES435B–APRIL 2003–REVISED SEPTEMBER 2004
OPERATING CHARACTERISTICS(1)
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
One fA = 10 MHz,
One fB = 10 MHz,
TOE = GND,
A outputs enabled,
Q outputs disabled,
One A output switching
12
14
19
LOE = VCC
,
DIR = GND,
CL = 0 pF
One fA = 10 MHz,
One fB = 10 MHz,
TOE = GND,
B outputs enabled,
Q outputs disabled,
One B output switching
12
14
21
LOE = VCC
,
DIR = GND,
CL = 0 pF
(2)
Cpd
Power dissipation
pF
(each output) capacitance
One fA = 10 MHz,
One fLE = 20 MHz,
One fQ = 10 MHz,
Q outputs enabled,
A and B I/Os isolated,
One Q output switching
11
7
13
8
19
12
11
TOE = VCC
,
LOE = GND,
CL = 0 pF
One fD = 10 MHz,
One fY = 10 MHz,
One Y output switching,
A and B I/Os isolated,
Q outputs disabled
TOE = VCC
,
LOE = VCC
,
CL = 0 pF
One fA = 10 MHz,
One fLE = 20 MHz,
fQ not switching,
A and B I/Os isolated,
Q outputs disabled,
One LE and one A data
input switching
Power dissipation
capacitance
Cpd (Z)
4
5
pF
pF
TOE = VCC,
LOE = VCC
,
CL = 0 pF
fA not switching,
One fLE = 20 MHz,
fQ not switching,
A and B I/Os isolated,
Q outputs disabled,
One LE input switching
(3)
Cpd
Power dissipation
capacitance
6
7
9
(each LE)
TOE = VCC,
LOE = VCC
,
CL = 0 pF
(1) Total device Cpd for multiple (m) outputs switching and (n) LE inputs switching = [m * Cpd (each output)] + [n * Cpd (each LE)].
(2) Cpd (each output) is the Cpd for each data bit (input and output circuitry) when it operates at 10 MHz (Note: the LE is operating at
20 MHz in this test, but its ICC component has been subtracted).
(3) Cpd (each LE) is the Cpd for the clock circuitry only when it operates at 20 MHz.
7
SN74ALVCH16973
8-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH
WITH FOUR INDEPENDENT BUFFERS
www.ti.com
SCES435B–APRIL 2003–REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
S1
GND
t
Open
V
LOAD
GND
pd
/t
/t
C
L
t
t
PLZ PZL
R
L
(see Note A)
PHZ PZH
LOAD CIRCUIT
INPUT
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V
V
V
2.7 V
V
/2
/2
2 × V
2 × V
6 V
1 kΩ
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
≤2 ns
≤2 ns
≤2.5 ns
30 pF
30 pF
50 pF
CC
CC
CC
2.5 V ± 0.2 V
3.3 V ± 0.3 V
V
CC
CC
CC
1.5 V
t
w
V
I
V
I
V
M
V
M
Input
Timing
Input
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
I
Output
Control
(low-level
enabling)
Data
Input
V
I
V
V
M
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at V
LOAD
(see Note B)
V
V
/2
LOAD
V
I
V
M
Input
V
M
V
M
V + V
∆
OL
0 V
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− V
∆
V
M
Output
V
M
V
M
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
8
PACKAGE OPTION ADDENDUM
www.ti.com
24-Feb-2006
PACKAGING INFORMATION
Orderable Device
74ALVCH16973DGGRE4
74ALVCH16973DGVRE4
74ALVCH16973DLG4
74ALVCH16973DLRG4
SN74ALVCH16973DGGR
SN74ALVCH16973DGVR
SN74ALVCH16973DL
SN74ALVCH16973DLR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
48
48
48
48
48
48
48
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
SSOP
SSOP
TSSOP
TVSOP
SSOP
SSOP
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGG
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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