SN74ALVCH373DGV [TI]
OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS; 八路透明D类锁存器与三态输出
| 型号： | SN74ALVCH373DGV |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS |
| 文件： | 总12页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇꢈ ꢉꢂ ꢉ
ꢊ ꢇꢋꢄꢅ ꢋ ꢌꢄꢁꢀ ꢍꢄꢌꢎ ꢁꢋ ꢏꢐꢋ ꢑꢍ ꢎ ꢅꢄꢋꢇ ꢈ
ꢒ ꢓꢋ ꢈ ꢉ ꢐꢀꢋꢄꢋ ꢎ ꢊ ꢔꢋ ꢍꢔ ꢋꢀ
SCES116G − JULY 1997 − REVISED AUGUST 2003
DGV, DW, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
Operates From 1.65 V to 3.6 V
Max t of 3.3 ns at 3.3 V
pd
24-mA Output Drive at 3.3 V
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
1
2
3
4
5
6
7
8
9
20
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 LE
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
GND 10
− 1000-V Charged-Device Model (C101)
description/ordering information
This octal transparent D-type latch is designed for 1.65-V to 3.6-V V
operation.
CC
The SN74ALVCH373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74ALVCH373DW
SN74ALVCH373DWR
SN74ALVCH373PWR
SN74ALVCH373DGVR
SN74ALVCH373GQNR
SN74ALVCH373ZQNR
SOIC − DW
ALVCH373
Tape and reel
Tape and reel
Tape and reel
TSSOP − PW
TVSOP − DGV
VB373
VB373
−40°C to 85°C
VFBGA − GQN
Tape and reel
VB373
VFBGA − ZQN (Pb-free)
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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ꢜ ꢠ ꢝ ꢜꢕ ꢖꢪ ꢘꢗ ꢛ ꢣꢣ ꢡꢛ ꢙ ꢛ ꢚ ꢠ ꢜ ꢠ ꢙ ꢝ ꢥ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢇ ꢈ ꢉ ꢂꢉ
ꢊꢇ ꢋꢄ ꢅ ꢋ ꢌ ꢄꢁ ꢀꢍꢄꢌ ꢎꢁ ꢋ ꢏꢐꢋ ꢑ ꢍꢎ ꢅꢄꢋꢇ ꢈ
ꢒꢓ ꢋ ꢈ ꢉ ꢐꢀꢋꢄꢋ ꢎ ꢊꢔꢋ ꢍ ꢔꢋꢀ
SCES116G − JULY 1997 − REVISED AUGUST 2003
GQN OR ZQN PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
1
2
3
4
A
B
C
D
E
1Q
2D
OE
7D
2Q
5D
4Q
V
8Q
8D
7Q
6D
5Q
A
B
C
D
E
CC
1D
6Q
3D
LE
3Q
4D
GND
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)
1
OE
11
LE
C1
1D
2
1Q
3
1D
To Seven Other Channels
Pin numbers shown are for the DGV, DW, and PW packages.
2
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ꢒ ꢓꢋ ꢈ ꢉ ꢐꢀꢋꢄꢋ ꢎ ꢊ ꢔꢋ ꢍꢔ ꢋꢀ
SCES116G − JULY 1997 − REVISED AUGUST 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN
1.65
MAX
UNIT
V
Supply voltage
3.6
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
0.65 × V
1.7
CC
V
High-level input voltage
V
V
2
0.35 × V
0.7
CC
V
IL
Low-level input voltage
0.8
V
V
Input voltage
0
0
V
V
V
V
I
CC
Output voltage
O
CC
−4
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
−12
−12
−24
4
I
High-level output current
Low-level output current
mA
mA
OH
OL
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
12
12
24
5
I
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
A
−40
85
°C
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢇ ꢈ ꢉ ꢂꢉ
ꢊꢇ ꢋꢄ ꢅ ꢋ ꢌ ꢄꢁ ꢀꢍꢄꢌ ꢎꢁ ꢋ ꢏꢐꢋ ꢑ ꢍꢎ ꢅꢄꢋꢇ ꢈ
ꢒꢓ ꢋ ꢈ ꢉ ꢐꢀꢋꢄꢋ ꢎ ꢊꢔꢋ ꢍ ꢔꢋꢀ
SCES116G − JULY 1997 − REVISED AUGUST 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
−0.2
MAX
UNIT
V
CC
I
I
I
= −100 µA
= −4 mA
= −6 mA
1.65 V to 3.6 V
1.65 V
2.3 V
V
OH
OH
OH
CC
1.2
2
2.3 V
1.7
2.2
2.4
2
V
OH
V
2.7 V
I
= −12 mA
OH
3 V
I
I
I
I
= −24 mA
= 100 µA
= 4 mA
3 V
OH
OL
OL
OL
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
0.7
0.4
0.55
5
= 6 mA
V
OL
V
2.3 V
I
= 12 mA
= 24 mA
OL
OL
2.7 V
I
3 V
I
I
V = V
or GND
3.6 V
µA
I
CC
V = 0.58 V
1.65 V
1.65 V
2.3 V
25
−25
45
I
V = 1.07 V
I
V = 0.7 V
I
V = 1.7 V
I
2.3 V
−45
75
I
µA
I(hold)
V = 0.8 V
I
3 V
V = 2 V
I
3 V
−75
‡
V = 0 to 3.6 V
3.6 V
500
10
I
I
I
V = V
O CC
or GND
or GND,
3.6 V
µA
µA
µA
OZ
V = V
I CC
I
O
= 0
3.6 V
20
CC
∆I
CC
One input at V
CC
− 0.6 V,
Other inputs at V
CC
or GND
3 V to 3.6 V
750
Control inputs
Data inputs
Outputs
4.5
5
C
V = V
CC
or GND
3.3 V
3.3 V
pF
pF
i
I
C
V
= V
or GND
= 3.3 V, T = 25°C.
7.5
o
O CC
†
‡
All typical values are at V
CC
A
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V
= 2.5 V
V
= 3.3 V
CC
0.2 V
CC
0.3 V
V
= 1.8 V
MAX
V
= 2.7 V
MAX
CC
CC
UNIT
MIN
3.8
1.3
0.5
MIN MAX
MIN
3.3
0.5
1.7
MIN MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
3.3
0.5
1.3
3.3
0.5
1.2
ns
ns
ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢒ ꢓꢋ ꢈ ꢉ ꢐꢀꢋꢄꢋ ꢎ ꢊ ꢔꢋ ꢍꢔ ꢋꢀ
SCES116G − JULY 1997 − REVISED AUGUST 2003
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
0.15 V
CC
0.2 V
CC
0.3 V
V
= 2.7 V
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
6.3
6.1
8.3
7
MIN
MAX
4
MIN
MAX
4
MIN
MAX
3.6
D
1.7
2
1
1
1
1
Q
t
pd
ns
LE
OE
OE
3.8
5.4
4.4
3.7
5.4
4.4
3.3
t
t
3.4
1.6
1.9
1
1.6
1
4.8
ns
ns
Q
Q
en
4.4
dis
operating characteristics, T = 25°C
A
V
= 1.8 V
CC
TYP
V
= 2.5 V
CC
TYP
V = 3.3 V
CC
TEST
CONDITIONS
PARAMETER
UNIT
TYP
Outputs enabled
Outputs disabled
31
7
33
7
37
9
Power dissipation capacitance
per latch
C = 0,
L
f = 10 MHz
C
pF
pd
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆꢇ ꢈ ꢉ ꢂꢉ
ꢊꢇ ꢋꢄ ꢅ ꢋ ꢌ ꢄꢁ ꢀꢍꢄꢌ ꢎꢁ ꢋ ꢏꢐꢋ ꢑ ꢍꢎ ꢅꢄꢋꢇ ꢈ
ꢒꢓ ꢋ ꢈ ꢉ ꢐꢀꢋꢄꢋ ꢎ ꢊꢔꢋ ꢍ ꢔꢋꢀ
SCES116G − JULY 1997 − REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
/t
C
t
t
V
L
PLZ PZL
LOAD
GND
R
L
(see Note A)
PHZ PZH
LOAD CIRCUIT
INPUT
V
CC
V
M
V
C
R
L
V
LOAD
L
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 0.2 V
2.7 V
V
V
V
/2
/2
2 × V
2 × V
6 V
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
30 pF
30 pF
50 pF
50 pF
CC
CC
CC
V
CC
0.15 V
0.3 V
0.3 V
CC
CC
2.7 V
2.7 V
1.5 V
1.5 V
3.3 V 0.3 V
6 V
t
w
V
I
V
I
V
M
V
M
Input
Timing
Input
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
I
Output
Control
(low-level
enabling)
Data
Input
V
I
V
V
M
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
+ V
Output
Waveform 1
V
V
/2
LOAD
V
I
V
M
Input
V
M
V
M
S1 at V
(see Note B)
V
OL
LOAD
∆
0 V
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− V
∆
V
M
Output
V
M
V
M
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPBG133C – APRIL 2000 – REVISED AUGUST 2002
GQN (R-PBGA-N20)
PLASTIC BALL GRID ARRAY
1,95 TYP
3,10
2,90
0,65
0,325
E
D
C
B
A
4,10
3,90
2,60
1
2
3
4
A1 Corner
Bottom View
1,00 MAX
0,08
Seating Plane
0,25
0,15
0,45
20×
0,35
M
0,05
4200704/D 07/2002
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar Juniort configuration
D. Falls within JEDEC MO-225 variation BC.
E. This package is tin-lead (SnPb). Refer to the 20 ZQN package (drawing 4204492) for lead-free.
MicroStar Junior is a trademark of Texas Instruments.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPBG297 – JULY 2002
ZQN (R-PBGA-N20)
PLASTIC BALL GRID ARRAY
1,95
0,65
3,10
2,90
0,325
E
D
C
B
A
4,10
3,90
2,60
1
2
3
4
Bottom View
A1 Corner
1,00 Max
0,08
Seating Plane
0,25
0,15
0,45
0,35
20×
0,05
M
4204492/A 06/2002
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar Junior configuration.
D. Fall within JEDEC MO-225 variation BC.
E. This package is lead-free. Refer to the 20 GQN package (drawing 4200704) for tin-lead )SnPb).
MicroStar Junior is a trademark of Texas Instruments.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSOI003E – JANUARY 1995 – REVISED SEPTEMBER 2001
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
9
0.050 (1,27)
16
0.010 (0,25)
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0°– 8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.012 (0,30)
0.004 (0,10)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
18
20
24
0.610
28
DIM
0.410
0.462
0.510
0.710
(18,03)
A MAX
(10,41) (11,73) (12,95) (15,49)
0.400
0.453
0.500
0.600
0.700
(17,78)
A MIN
(10,16) (11,51) (12,70) (15,24)
4040000/E 08/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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