SN74ALVTH162245DL [TI]
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS;
| 型号： | SN74ALVTH162245DL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 信息通信管理 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331A – APRIL 2000 – REVISED APRIL 2002
SN54ALVTH162245 . . . WD PACKAGE
SN74ALVTH162245 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus Design for
2.5-V and 3.3-V Operation and Low
Static-Power Dissipation
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
2
3
3.6-V V
)
CC
4
Typical V
<0.8 V at V
(Output Ground Bounce)
5
OLP
CC
= 3.3 V, T = 25°C
6
A
7
V
V
High Drive
CC
CC
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
– A Port = –12/12 mA at 3.3-V V
– B port = –32/64 mA at 3.3-V V
CC
CC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I
and Power-Up 3-State Support Hot
off
Insertion
Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
A-Port Outputs Have Equivalent 30-Ω
Series Resistors, So No External Resistors
Are Required
V
V
CC
CC
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
2B5
2B6
GND
2B7
2B8
2A5
2A6
GND
2A7
2A8
2OE
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
2DIR
description
The’ALVTH162245 devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for 2.5-V or 3.3-V
operation, but with the capability to provide a TTL interface to a 5-V system environment.
V
CC
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission
from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively
isolated.
The A-port outputs, which are designed to source or sink up to 12 mA, include equivalent 30-Ω series resistors
to reduce overshoot and undershoot.
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup
or pulldown resistors with the bus-hold circuitry is not recommended.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331A – APRIL 2000 – REVISED APRIL 2002
description (continued)
When V
is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.2 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
SN74ALVTH162245 . . . GQL PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1DIR
1B2
1B4
1B6
1B8
2B1
2B3
2B5
2B7
2DIR
NC
NC
NC
NC
1OE
1A2
1A4
1A6
1A8
2A1
2A3
2A5
2A7
2OE
A
B
C
D
1B1
1B3
1B5
1B7
2B2
2B4
2B6
2B8
NC
GND
GND
1A1
1A3
1A5
1A7
2A2
2A4
2A6
2A8
NC
V
CC
V
CC
GND
GND
E
F
G
H
J
GND
GND
G
H
J
V
CC
V
CC
GND
NC
GND
NC
K
K
NC – No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
SSOP – DL
Tape and reel SN74ALVTH162245LR
Tape and reel SN74ALVTH162245GR
Tape and reel SN74ALVTH162245VR
Tape and reel SN74ALVTH162245QR
ALVTH162245
ALVTH162245
VT2245
TSSOP – DGG
TVSOP – DGV
VFBGA – GQL
–40°C to 85°C
–55°C to 125°C
CFP – WD
Tube
SNJ54ALVTH162245WD
SNJ54ALVTH162245WD
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331A – APRIL 2000 – REVISED APRIL 2002
logic diagram (positive logic)
1
24
1DIR
2DIR
2A1
48
25
1OE
1B1
2OE
47
36
1A1
2
13
2B1
To Seven Other Channels
Pin numbers shown are for the DGG, DGV, DL, and WD packages.
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Output current in the low state, I : SN54ALVTH162245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ALVTH162245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Output current in the high state, I : SN54ALVTH162245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –48 mA
O
SN74ALVTH162245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –64 mA
Continuous current through V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331A – APRIL 2000 – REVISED APRIL 2002
recommended operating conditions, V
= 2.5 V ± 0.2 V (see Note 3)
CC
SN54ALVTH162245
SN74ALVTH162245
UNIT
MIN
2.3
TYP
MAX
MIN
2.3
TYP
MAX
V
CC
V
IH
V
IL
V
I
Supply voltage
2.7
2.7
V
V
V
V
High-level input voltage
Low-level input voltage
1.7
1.7
0.7
5.5
–6
–6
6
0.7
5.5
–8
–8
12
8
Input voltage
0
V
CC
0
V
CC
High-level output current (A port)
High-level output current (B port)
Low-level output current (A port)
Low-level output current (B port)
I
mA
OH
6
I
mA
OL
Low-level output current;
18
10
24
10
current duty cycle ≤ 50%; f ≥ 1 kHz (B port)
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
ns/V
µs/V
°C
200
200
CC
T
A
Operating free-air temperature
–55
125
–40
85
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
recommended operating conditions, V
= 3.3 V ± 0.3 V (see Note 3)
CC
SN54ALVTH162245
SN74ALVTH162245
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
V
V
V
V
Supply voltage
3
3.6
3
3.6
V
V
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
2
0
2
0
0.8
5.5
–8
0.8
5.5
–12
–32
12
Input voltage
V
CC
V
CC
High-level output current (A port)
High-level output current (B port)
Low-level output current (A port)
Low-level output current (B port)
I
mA
OH
–24
8
24
32
I
mA
OL
Low-level output current;
current duty cycle ≤ 50%; f ≥ 1 kHz (B port)
48
10
64
10
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
ns/V
µs/V
°C
200
200
CC
T
A
Operating free-air temperature
–55
125
–40
85
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331A – APRIL 2000 – REVISED APRIL 2002
electrical characteristics over recommended operating free-air temperature range,
= 2.5 V ± 0.2 V (unless otherwise noted)
V
CC
SN54ALVTH162245
SN74ALVTH162245
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
= 2.3 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 2.3 V to 2.7 V,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –6 mA
= –8 mA
= –100 µA
= –6 mA
= –8 mA
= 100 µA
= 6 mA
V
V
–0.2
V
V
–0.2
CC
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
OL
OL
CC
CC
A port
1.7
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3 V
1.7
V
OH
V
= 2.3 V to 2.7 V,
= 2.3 V
–0.2
–0.2
CC
CC
B port
A port
1.7
1.7
= 2.3 V to 2.7 V,
= 2.3 V
0.2
0.4
0.2
= 12 mA
= 100 µA
= 6 mA
0.4
0.2
= 2.3 V to 2.7 V,
0.2
0.4
V
OL
V
B port
= 8 mA
0.4
V
CC
= 2.3 V
= 18 mA
= 24 mA
0.5
0.5
±1
V
V
= 2.7 V,
V = GND
I
±1
10
20
1
CC
Control inputs
A or B ports
= 0 or 2.7 V,
V = 5.5 V
I
10
CC
I
I
V = 5.5 V
I
20
µA
V
CC
= 2.7 V
V = V
I CC
1
V = 0
I
–5
–5
I
I
I
I
I
I
V
V
V
V
V
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
µA
µA
µA
µA
off
CC
CC
CC
CC
CC
CC
CC
I
O
‡
= 2.3 V,
= 2.3 V,
= 2.7 V,
= 2.7 V,
= 2.3 V,
V = 0.7 V
I
115
115
BHL
§
V = 1.7 V
I
–10
–10
BHH
¶
V = 0 to V
300
–300
300
–300
BHLO
I
CC
CC
#
V = 0 to V
I
BHHO
||
V
O
= 5.5 V
125
125
EX
≤ 1.2 V, V = 0.5 V to V
CC
,
O
CC
±100
±100
µA
I
OZ(PU/PD)
CC
V = GND or V , OE = don’t care
I
Outputs high
Outputs low
0.04
2.3
0.04
3.5
8
0.1
4.5
0.1
0.04
2.3
0.04
3.5
8
0.1
4.5
0.1
V
I
= 2.7 V,
= 0,
CC
O
I
mA
V = V
I
or GND
CC
Outputs disabled
C
C
V
V
= 2.5 V,
= 2.5 V,
V = 2.5 V or 0
I
pF
pF
i
CC
V
O
= 2.5 V or 0
io
CC
†
‡
All typical values are at V
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
= 2.5 V, T = 25°C.
A
CC
should be measured after lowering V to GND and
BHL IN
IL
then raising it to V max.
IL
§
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
¶
#
||
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
Current into an output in the high state when V > V
High-impedance state during power up or power down
O
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331A – APRIL 2000 – REVISED APRIL 2002
electrical characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted)
CC
SN54ALVTH162245
SN74ALVTH162245
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
= 3 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 3 V to 3.6 V,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –8 mA
= –12 mA
= –100 µA
= –24 mA
= –32 mA
= 100 µA
= 8 mA
V
V
–0.2
V
V
–0.2
CC
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
OL
OL
CC
CC
A port
2
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
2
V
OH
V
= 3 V to 3.6 V,
= 3 V
–0.2
–0.2
CC
CC
B port
A port
2
2
= 3 V to 3.6 V,
= 3 V
0.2
?
0.2
= 12 mA
= 100 µA
= 24 mA
= 32 mA
= 48 mA
= 64 mA
0.8
0.2
= 3 V to 3.6 V,
0.2
0.5
V
OL
V
B port
0.5
V
CC
= 3 V
0.55
0.55
±1
V
V
= 3.6 V,
V = V
I
or GND
±1
10
20
1
CC
CC
Control inputs
A or B ports
= 0 or 3.6 V,
V = 5.5 V
I
10
CC
I
I
V = 5.5 V
I
20
µA
V
CC
= 3.6 V
V = V
I CC
1
V = 0
I
–5
–5
I
I
I
I
I
I
V
V
V
V
V
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
µA
µA
µA
µA
off
CC
CC
CC
CC
CC
CC
CC
I
O
‡
= 3 V,
= 3 V,
= 3.6 V,
= 3.6 V,
= 3 V,
V = 0.8 V
I
75
75
BHL
§
V = 2 V
I
–75
–75
BHH
¶
V = 0 to V
500
500
BHLO
I
CC
CC
#
V = 0 to V
I
–500
–500
BHHO
||
V
O
= 5.5 V
125
125
EX
≤ 1.2 V, V = 0.5 V to V
CC
,
O
CC
±100
±100
µA
mA
mA
I
OZ(PU/PD)
CC
V = GND or V , OE = don’t care
I
Outputs high
Outputs low
0.07
3.2
0.1
5
0.07
3.2
0.1
5
V
I
= 3.6 V,
= 0,
CC
O
I
V = V
I
or GND
CC
Outputs disabled
0.07
0.1
0.07
0.1
V
= 3 V to 3.6 V, One input at V – 0.6 V,
CC
CC
Other inputs at V
0.2
0.2
∆I
CC
or GND
CC
C
C
V
V
= 3.3 V,
= 3.3 V,
V = 3.3 V or 0
3.5
8
3.5
8
pF
pF
i
CC
I
V
O
= 3.3 V or 0
io
CC
†
‡
All typical values are at V
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
= 3.3 V, T = 25°C.
A
CC
should be measured after lowering V to GND and
BHL IN
IL
then raising it to V max.
IL
§
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
An external driver must source at least I
¶
#
||
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
Current into an output in the high state when V > V
O
CC
High-impedance state during power up or power down
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331A – APRIL 2000 – REVISED APRIL 2002
switching characteristics over recommended operating free-air temperature range, C = 30 pF,
L
V
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
CC
SN54ALVTH162245 SN74ALVTH162245
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
0.3
0.5
1.1
1.1
2
MAX
3.6
3.5
4.3
3.8
5.6
4.4
5.1
4.1
4.9
4.3
4.8
4.1
MIN
0.3
0.5
1.1
1.1
2
MAX
3.6
3.5
4.3
3.8
5.6
4.4
5.1
4.1
4.9
4.3
4.8
4.1
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
A
B
A
A
B
A
B
ns
ns
OE
OE
OE
1.8
1.5
1.5
1.9
1.5
1.9
1.5
1.8
1.5
1.5
1.9
1.5
1.9
1.5
ns
ns
B
ns
OE
switching characteristics over recommended operating free-air temperature range, C = 50 pF,
L
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
CC
SN54ALVTH162245 SN74ALVTH162245
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
0.5
0.5
1
MAX
3.1
3
MIN
0.5
0.5
1
MAX
3.1
3
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
A
B
A
A
B
A
3.7
3.4
4.7
3.9
3.8
3.4
5
3.7
3.4
4.7
3.9
3.8
3.4
5
B
ns
1
1
1.4
1.4
1
1.4
1.4
1
ns
OE
OE
OE
ns
0.7
2.4
2.6
2.4
2.3
0.7
2.4
2.6
2.4
2.3
ns
4.9
4.7
4.8
4.9
4.7
4.8
B
ns
OE
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331A – APRIL 2000 – REVISED APRIL 2002
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
S1
R
L
TEST
S1
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
t
2 × V
CC
GND
C
PLZ PZL
L
R
L
(see Note A)
/t
PHZ PZH
C
V
∆
R
V
CC
L
L
2.5 V ±0.2 V
3.3 V ±0.3 V
500 Ω
500 Ω
0.15 V
0.3 V
30 pF
50 pF
LOAD CIRCUIT
V
CC
Timing Input
V
CC
/2
0 V
t
w
t
t
h
su
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
V
CC
/2
V
CC
/2
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
Input
0 V
0 V
t
t
t
t
t
PHL
/2
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
V
V
V
OH
CC
V
/2
/2
V
V
/2
/2
V
CC
CC
Output
CC
V
V
+ V
∆
S1 at 2 × V
(see Note B)
OL
CC
OL
OL
t
t
t
PLH
/2
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– V
OH
∆
V
CC
V
CC
CC
Output
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
SN74ALVTH16240DLR
ALVT SERIES, QUAD 4-BIT DRIVER, INVERTED OUTPUT, PDSO48, GREEN, PLASTIC, SSOP-48
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