SN74ALVTH16240VR [TI]
ALVT SERIES, QUAD 4-BIT DRIVER, INVERTED OUTPUT, PDSO48, GREEN, TVSOP-48;
| 型号： | SN74ALVTH16240VR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ALVT SERIES, QUAD 4-BIT DRIVER, INVERTED OUTPUT, PDSO48, GREEN, TVSOP-48 驱动 信息通信管理 光电二极管 输出元件 逻辑集成电路 电视 |
| 文件： | 总17页 (文件大小：613K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALVTH16240, SN74ALVTH16240
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES138A – JULY 1998 – REVISED JANUARY 1999
SN54ALVTH16240 . . . WD PACKAGE
SN74ALVTH16240 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus Design for
2.5-V and 3.3-V Operation and Low Static
Power Dissipation
1OE
1Y1
1Y2
GND
1Y3
1Y4
1
2
3
4
5
6
7
8
9
48 2OE
47 1A1
46 1A2
45 GND
44 1A3
43 1A4
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V V
)
CC
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
High Drive (–24/24 mA at 2.5-V and
–32/64 mA at 3.3-V V
V
42
V
CC
CC
)
2Y1
2Y2
41 2A1
40 2A2
39 GND
38 2A3
37 2A4
36 3A1
35 3A2
34 GND
33 3A3
32 3A4
CC
Power Off Disables Outputs, Permitting
Live Insertion
GND 10
2Y3 11
2Y4 12
3Y1 13
3Y2 14
GND 15
3Y3 16
3Y4 17
High-Impedance State During Power Up
and Power Down Prevents Driver Conflict
Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
Auto3-State Eliminates Bus Current
Loading When Output Exceeds V
+ 0.5 V
CC
V
18
31
V
CC
CC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
4Y1 19
4Y2 20
GND 21
4Y3 22
4Y4 23
4OE 24
30 4A1
29 4A2
28 GND
27 4A3
26 4A4
25 3OE
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model; and Exceeds 1000 V
Using Charged-Device Model, Robotic
Method
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
description
The ’ALVTH16240 devices are 16-bit buffers/line drivers designed for 2.5-V or 3.3-V V
the capability to provide a TTL interface to a 5-V system environment.
operation, but with
CC
These devices are designed specifically to improve both the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16240, SN74ALVTH16240
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES138A – JULY 1998 – REVISED JANUARY 1999
description (continued)
The devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The devices provide
inverting outputs and symmetrical active-low output-enable (OE) inputs.
When V
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH16240 is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ALVTH16240 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
L
H
Z
H
X
†
logic symbol
1
1OE
2OE
3OE
EN1
EN2
EN3
EN4
48
25
24
4OE
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
3
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
1
1
1
1
2
3
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1
4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16240, SN74ALVTH16240
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES138A – JULY 1998 – REVISED JANUARY 1999
logic diagram (positive logic)
1
25
1OE
3OE
3A1
47
2
3
5
6
36
35
33
32
13
14
16
17
1A1
1Y1
1Y2
1Y3
1Y4
3Y1
3Y2
3Y3
3Y4
46
1A2
3A2
3A3
3A4
44
1A3
43
1A4
48
24
30
2OE
4OE
4A1
41
8
9
19
20
22
23
2A1
2Y1
2Y2
2Y3
2Y4
4Y1
4Y2
4Y3
4Y4
40
29
27
26
2A2
4A2
4A3
4A4
38
11
12
2A3
37
2A4
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Output current in the low state, I : SN54ALVTH16240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ALVTH16240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Output current in the high state, I : SN54ALVTH16240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –48 mA
O
SN74ALVTH16240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16240, SN74ALVTH16240
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES138A – JULY 1998 – REVISED JANUARY 1999
recommended operating conditions, V
= 2.5 V ± 0.2 V (see Note 3)
CC
SN54ALVTH16240
SN74ALVTH16240
UNIT
MIN
2.3
TYP
MAX
MIN
2.3
TYP
MAX
V
V
V
V
Supply voltage
2.7
2.7
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
1.7
1.7
0.7
5.5
–6
6
0.7
5.5
–8
8
V
0
V
CC
0
V
CC
V
I
I
High-level output current
Low-level output current
mA
OH
I
mA
OL
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz
18
10
24
10
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
ns/V
µs/V
°C
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
recommended operating conditions, V
= 3.3 V ± 0.3 V (see Note 3)
CC
SN54ALVTH16240
SN74ALVTH16240
UNIT
MIN
3
TYP
MAX
MIN
3
TYP
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
2
2
0.8
5.5
–24
24
0.8
5.5
–32
32
V
0
V
CC
0
V
CC
V
I
I
High-level output current
Low-level output current
mA
OH
I
mA
OL
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz
48
64
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
10
10
ns/V
µs/V
°C
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16240, SN74ALVTH16240
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES138A – JULY 1998 – REVISED JANUARY 1999
electrical characteristics over recommended operating free-air temperature range,
= 2.5 V ± 0.2 V (unless otherwise noted)
V
CC
SN54ALVTH16240
SN74ALVTH16240
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 2.3 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 2.3 V to 2.7 V,
I
I
I
I
I
I
I
I
= –100 µA
= –6 mA
= –8 mA
= 100 µA
= 6 mA
V
–0.2
CC
1.8
V
–0.2
CC
OH
OH
OH
OL
OL
OL
OL
OL
CC
V
V
OH
V
= 2.3 V
CC
CC
1.8
V
= 2.3 V to 2.7 V,
0.2
0.4
0.2
0.4
V
OL
= 8 mA
V
CC
= 2.3 V
= 18 mA
= 24 mA
0.5
0.5
±1
V
V
= 2.7 V,
V = V
I
or GND
±1
10
10
1
CC
CC
Control inputs
Data inputs
= 0 or 2.7 V,
V = 5.5 V
I
10
CC
I
I
V = 5.5 V
I
10
µA
V
CC
= 2.7 V
V = V
I CC
1
V = 0
I
–5
–5
I
I
I
I
I
I
V
V
V
V
V
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
µA
µA
µA
µA
off
CC
CC
CC
CC
CC
CC
CC
I
O
‡
= 2.3 V,
= 2.3 V,
= 2.7 V,
= 2.7 V,
= 2.3 V,
V = 0.7 V
I
115
–10
115
–10
BHL
§
V = 1.7 V
I
BHH
¶
V = 0 to V
300
–300
300
–300
BHLO
I
CC
CC
#
V = 0 to V
I
BHHO
||
V
O
= 5.5 V
125
125
EX
≤ 1.2 V, V = 0.5 V to V
CC
,
O
CC
±100
±100
µA
µA
I
OZ(PU/PD)
OZH
V = GND or V , OE = don’t care
I
V
O
= 2.3 V,
I
V
CC
= 2.7 V
5
5
V = 0.7 V or 1.7 V
I
V
= 0.5 V,
O
I
V
= 2.7 V
= 2.7 V,
–5
–5
µA
OZL
CC
CC
CC
V = 0.7 V or 1.7 V
I
Outputs high
Outputs low
0.04
2.3
0.04
3.5
6
0.1
4.5
0.1
0.04
2.3
0.04
3.5
6
0.1
4.5
0.1
V
I
I
mA
= 0,
O
V = V
or GND
I
CC
Outputs disabled
C
C
V
V
= 2.5 V,
= 2.5 V,
V = 2.5 V or 0
I
pF
pF
i
CC
V
O
= 2.5 V or 0
o
CC
†
‡
All typical values are at V
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
= 2.5 V, T = 25°C.
A
CC
should be measured after lowering V to GND and
BHL IN
IL
then raising it to V max.
IL
§
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
¶
#
||
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
Current into an output in the high state when V > V
High-impedance state during power up or power down
O
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16240, SN74ALVTH16240
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES138A – JULY 1998 – REVISED JANUARY 1999
electrical characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted)
CC
SN54ALVTH16240
SN74ALVTH16240
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 3 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 3 V to 3.6 V,
I
I
I
I
I
I
I
I
I
= –100 µA
= –24 mA
= –32 mA
= 100 µA
= 16 mA
= 24 mA
= 32 mA
= 48 mA
= 64 mA
V
CC
–0.2
2
V
CC
–0.2
2
CC
OH
OH
OH
OL
OL
OL
OL
OL
OL
V
V
OH
V
= 3 V
CC
CC
V
= 3 V to 3.6 V,
0.2
0.5
0.2
0.4
V
OL
V
CC
= 3 V
0.5
0.55
0.55
±1
V
V
= 3.6 V,
V = V
I
or GND
±1
10
10
1
CC
CC
Control inputs
Data inputs
= 0 or 3.6 V,
V = 5.5 V
I
10
CC
I
I
V = 5.5 V
I
10
µA
V
CC
= 3.6 V
V = V
I CC
1
V = 0
I
–5
–5
I
I
I
I
I
I
V
V
V
V
V
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
µA
µA
µA
µA
off
CC
CC
CC
CC
CC
CC
CC
I
O
‡
= 3 V,
= 3 V,
= 3.6 V,
= 3.6 V,
= 3 V,
V = 0.8 V
I
75
75
BHL
§
V = 2 V
I
–75
500
–75
500
BHH
¶
V = 0 to V
BHLO
I
CC
CC
#
V = 0 to V
I
–500
–500
BHHO
||
V
O
= 5.5 V
125
125
EX
≤ 1.2 V, V = 0.5 V to V
CC
,
O
CC
±100
±100
µA
µA
I
OZ(PU/PD)
OZH
V = GND or V , OE = don’t care
I
V
O
= 3 V,
I
V
CC
= 3.6 V
5
5
V = 0.8 V or 2 V
I
V
= 0.5 V,
O
I
I
V
= 3.6 V
= 3.6 V,
–5
–5
µA
OZL
CC
CC
V = 0.8 V or 2 V
I
Outputs high
Outputs low
0.07
3.2
0.1
5.5
0.1
0.07
3.2
0.1
5
V
I
mA
mA
= 0,
CC
O
V = V
or GND
I
CC
Outputs disabled
0.07
0.07
0.1
V
= 3 V to 3.6 V, One input at V – 0.6 V,
CC
CC
Other inputs at V
0.4
0.4
∆I
CC
or GND
CC
C
C
V
V
= 3.3 V,
= 3.3 V,
V = 3.3 V or 0
3.5
6
3.5
6
pF
pF
i
CC
I
V
O
= 3.3 V or 0
o
CC
†
‡
All typical values are at V
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
= 3.3 V, T = 25°C.
A
CC
should be measured after lowering V to GND and
BHL IN
IL
then raising it to V max.
IL
§
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
¶
#
||
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
Current into an output in the high state when V > V
O
CC
High-impedance state during power up or power down
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16240, SN74ALVTH16240
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES138A – JULY 1998 – REVISED JANUARY 1999
switching characteristics over recommended operating free-air temperature range, C = 30 pF,
L
V
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
CC
SN54ALVTH16240 SN74ALVTH16240
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
1
MAX
3.8
3.6
5.4
4.3
4.8
3.6
MIN
1
MAX
3.7
3.5
5.3
4.2
4.7
3.5
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
1
1
1
1
ns
OE
OE
1
1
1
1
ns
1
1
switching characteristics over recommended operating free-air temperature range, C = 50 pF,
L
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
CC
SN54ALVTH16240 SN74ALVTH16240
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
1
MAX
3.4
3.3
3.8
3.2
5.1
4.2
MIN
1
MAX
3.3
3.2
3.7
3.1
5
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
1
1
1
1
ns
OE
OE
1
1
1.4
1.4
1.5
1.5
ns
4.1
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16240, SN74ALVTH16240
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES138A – JULY 1998 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16240, SN74ALVTH16240
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES138A – JULY 1998 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
V
= 3.3 V ± 0.3 V
CC
6 V
S1
Open
500 Ω
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
6 V
PLH PHL
/t
C
= 50 pF
t
L
PLZ PZL
500 Ω
(see Note A)
/t
GND
PHZ PZH
LOAD CIRCUIT
t
w
3 V
0 V
3 V
0 V
1.5 V
Input
1.5 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
3 V
0 V
Data
Input
3 V
0 V
1.5 V
1.5 V
1.5 V
1.5 V
Output Control
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
S1 at 6 V
3 V
V
3 V
0 V
1.5 V
1.5 V
1.5 V
Input
V
V
+ 0.3 V
OL
(see Note B)
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
≈ 0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
74ALVTH16240DLG4
SN74ALVTH16240DL
SN74ALVTH16240DLR
SN74ALVTH16240GR
SN74ALVTH16240VR
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SSOP
SSOP
DL
48
48
48
48
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
ALVTH16240
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DL
DL
25
Green (RoHS
& no Sb/Br)
-40 to 85
ALVTH16240
ALVTH16240
ALVTH16240
VT240
SSOP
1000
2000
2000
Green (RoHS
& no Sb/Br)
-40 to 85
TSSOP
TVSOP
DGG
DGV
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ALVTH16240DLR
SN74ALVTH16240GR
SN74ALVTH16240VR
SSOP
TSSOP
TVSOP
DL
48
48
48
1000
2000
2000
330.0
330.0
330.0
32.4
24.4
16.4
11.35 16.2
3.1
1.8
1.6
16.0
12.0
12.0
32.0
24.0
16.0
Q1
Q1
Q1
DGG
DGV
8.6
7.1
15.8
10.2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74ALVTH16240DLR
SN74ALVTH16240GR
SN74ALVTH16240VR
SSOP
TSSOP
TVSOP
DL
48
48
48
1000
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
55.0
45.0
38.0
DGG
DGV
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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