SN74ALVTH16501DGGR [TI]
ALVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, TSSOP-56;
| 型号： | SN74ALVTH16501DGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ALVT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, TSSOP-56 总线收发器 输出元件 |
| 文件： | 总11页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALVTH16501, SN74ALVTH16501
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES071D – JUNE 1996 – REVISED JANUARY 1999
SN54ALVTH16501 . . . WD PACKAGE
SN74ALVTH16501 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
OEAB
LEAB
A1
GND
A2
GND
CLKAB
B1
GND
B2
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
49
48
State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus Design for
2.5-V and 3.3-V Operation and Low Static
Power Dissipation
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
A3
B3
V
V
CC
CC
3.6-V V
)
CC
A4
A5
B4
B5
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A6 10
47 B6
A
GND
A7
GND
B7
11
12
46
45
High Drive (–24/24 mA at 2.5-V and
–32/64 mA at 3.3-V V
)
CC
A8 13
A9 14
44 B8
Power Off Disables Outputs, Permitting
Live Insertion
43 B9
A10 15
A11 16
A12 17
GND 18
A13 19
A14 20
A15 21
42 B10
41 B11
40 B12
39 GND
38 B13
37 B14
36 B15
High-Impedance State During Power Up
and Power Down Prevents Driver Conflict
Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
Auto3-State Eliminates Bus Current
Loading When Output Exceeds V
+ 0.5 V
V
22
35
V
CC
CC
CC
A16 23
34 B16
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
A17 24
33 B17
GND 25
A18 26
32 GND
31 B18
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
OEBA 27
LEBA 28
30 CLKBA
29 GND
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
description
The ’ALVTH16501 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V V operation, but
CC
with the capability to provide a TTL interface to a 5-V system environment.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the
B-port outputs are active. When OEAB is low, the B-port outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UBT and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16501, SN74ALVTH16501
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES071D – JUNE 1996 – REVISED JANUARY 1999
description (continued)
When V
is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
CC
However, toensurethehigh-impedancestateabove1.2V,OEBAshouldbetiedtoV throughapullupresistor
CC
and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined
by the current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH16501 is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ALVTH16501 is characterized for operation from –40°C to 85°C.
†
FUNCTION TABLE
INPUTS
OUTPUT
B
OEAB
LEAB
CLKAB
A
X
L
L
X
H
H
L
X
X
X
=
↑
Z
L
H
H
H
H
H
H
H
L
H
L
L
H
X
X
H
‡
B
0
§
B
0
L
H
L
L
†
‡
A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA, LEBA, and CLKBA.
Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was high before LEAB went low
§
Output level before the indicated steady-state input
conditions were established
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16501, SN74ALVTH16501
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES071D – JUNE 1996 – REVISED JANUARY 1999
logic diagram (positive logic)
1
OEAB
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
27
OEBA
3
A1
1D
C1
54
B1
CLK
1D
C1
CLK
To 17 Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V (see Note 1) . . . . . . . . . –0.5 V to 7 V
O
Output current in the low state, I : SN54ALVTH16501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ALVTH16501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Output current in the high state, I : SN54ALVTH16501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –48 mA
O
SN74ALVTH16501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16501, SN74ALVTH16501
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES071D – JUNE 1996 – REVISED JANUARY 1999
recommended operating conditions, V
= 2.5 V ± 0.2 V (see Note 3)
CC
SN54ALVTH16501
SN74ALVTH16501
UNIT
MIN
2.3
TYP
MAX
MIN
2.3
TYP
MAX
V
V
V
V
Supply voltage
2.7
2.7
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
1.7
1.7
0.7
5.5
–6
6
0.7
5.5
–8
8
V
0
V
CC
0
V
CC
V
I
I
High-level output current
Low-level output current
mA
OH
I
mA
OL
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz
18
10
24
10
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
ns/V
µs/V
°C
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
recommended operating conditions, V
= 3.3 V ± 0.3 V (see Note 3)
CC
SN54ALVTH16501
SN74ALVTH16501
UNIT
MIN
3
TYP
MAX
MIN
3
TYP
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
2
2
0.8
5.5
–24
24
0.8
5.5
–32
32
V
0
V
CC
0
V
CC
V
I
I
High-level output current
Low-level output current
mA
OH
I
mA
OL
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz
48
64
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
10
10
ns/V
µs/V
°C
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16501, SN74ALVTH16501
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES071D – JUNE 1996 – REVISED JANUARY 1999
electrical characteristics over recommended operating free-air temperature range,
= 2.5 V ± 0.2 V (unless otherwise noted)
V
CC
SN54ALVTH16501
SN74ALVTH16501
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 2.3 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 2.3 V to 2.7 V,
I
I
I
I
I
I
I
I
I
= –100 µA
= –6 mA
= –8 mA
= 100 µA
= 6 mA
V
–0.2
CC
1.8
V
–0.2
CC
OH
OH
OH
OL
OL
OL
OL
OL
CC
V
OH
V
= 2.3 V
CC
CC
1.8
V
= 2.3 V to 2.7 V,
0.2
0.4
0.2
0.4
V
V
= 8 mA
V
V
OL
V
CC
= 2.3 V
= 2.7 V
= 18 mA
= 24 mA
0.5
0.5
= 1 mA,
O
I
‡
V
CC
0.55
0.55
RST
V = V
or GND
CC
CC
V
V
= 2.7 V,
V = V
or GND
±1
10
10
1
±1
10
CC
I
Control inputs
A or B ports
= 0 or 2.7 V,
V = 5.5 V
I
CC
I
I
V = 5.5 V
I
10
µA
V
CC
= 2.7 V
V = V
I CC
1
V = 0
I
–5
–5
I
I
I
I
I
I
V
V
V
V
V
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
µA
µA
µA
µA
off
CC
CC
CC
CC
CC
CC
CC
I
O
§
= 2.3 V,
= 2.3 V,
= 2.7 V,
= 2.7 V,
= 2.3 V,
V = 0.7 V
I
115
–10
115
–10
BHL
¶
V = 1.7 V
I
BHH
#
V = 0 to V
300
–300
300
–300
BHLO
I
CC
CC
||
V = 0 to V
I
BHHO
EX
V
O
= 5.5 V
125
125
≤ 1.2 V, V = 0.5 V to V
CC
,
O
CC
±100
±100
µA
I
OZ(PU/PD)
CC
V = GND or V , OE = don’t care
I
Outputs high
Outputs low
0.04
2.5
0.1
4.5
0.1
0.04
2.5
0.1
4.5
0.1
V
I
= 2.7 V,
= 0,
CC
O
I
mA
V = V
I
or GND
CC
Outputs disabled
0.04
0.04
C
C
V
V
= 2.5 V,
= 2.5 V,
V = 2.5 V or 0
pF
pF
i
CC
I
V
O
= 2.5 V or 0
io
CC
†
‡
§
All typical values are at V
Data must not be loaded into the flip-flops/latches after applying power.
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
then raising it to V max.
IL
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
= 2.5 V, T = 25°C.
A
CC
should be measured after lowering V to GND and
IN
IL
BHL
¶
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
#
||
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
Current into an output in the high state when V > V
High-impedance state during power up or power down
O
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16501, SN74ALVTH16501
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES071D – JUNE 1996 – REVISED JANUARY 1999
electrical characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted)
CC
SN54ALVTH16501
SN74ALVTH16501
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 3 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 3 V to 3.6 V,
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –24 mA
= –32 mA
= 100 µA
= 16 mA
= 24 mA
= 32 mA
= 48 mA
= 64 mA
V
CC
–0.2
2
V
CC
–0.2
2
CC
OH
OH
OH
OL
OL
OL
OL
OL
OL
V
V
OH
V
= 3 V
CC
CC
V
= 3 V to 3.6 V,
0.2
0.5
0.2
0.4
V
V
OL
V
CC
= 3 V
0.5
0.55
0.55
0.55
= 1 mA,
O
‡
V
CC
= 3.6 V
0.55
V
RST
V = V
or GND
I
CC
V
V
= 3.6 V,
V = V
or GND
±1
10
10
1
±1
10
CC
I
CC
Control inputs
A or B ports
= 0 or 3.6 V,
V = 5.5 V
I
CC
I
I
V = 5.5 V
I
10
µA
V
CC
= 3.6 V
V = V
I CC
1
V = 0
I
–5
–5
I
I
I
I
I
I
V
V
V
V
V
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
µA
µA
µA
µA
off
CC
CC
CC
CC
CC
CC
CC
I
O
§
= 3 V,
= 3 V,
= 3.6 V,
= 3.6 V,
= 3 V,
V = 0.8 V
I
75
75
BHL
¶
V = 2 V
I
–75
500
–75
500
BHH
#
V = 0 to V
BHLO
I
CC
CC
||
V = 0 to V
I
–500
–500
BHHO
EX
V
O
= 5.5 V
125
125
≤ 1.2 V, V = 0.5 V to V
CC
,
O
CC
±100
±100
µA
mA
mA
I
OZ(PU/PD)
CC
V = GND or V , OE = don’t care
I
Outputs high
Outputs low
0.06
3.5
0.1
5
0.06
3.5
0.1
5
V
I
= 3.6 V,
= 0,
CC
O
I
V = V
I
or GND
CC
Outputs disabled
0.06
0.1
0.06
0.1
V
= 3 V to 3.6 V, One input at V – 0.6 V,
CC
CC
Other inputs at V
0.4
0.4
∆I
CC
◊
or GND
CC
C
C
V
V
= 3.3 V,
= 3.3 V,
V = 3.3 V or 0
pF
pF
i
CC
I
V
O
= 3.3 V or 0
io
CC
†
‡
§
All typical values are at V
Data must not be loaded into the flip-flops/latches after applying power.
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
then raising it to V max.
IL
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
= 3.3 V, T = 25°C.
A
CC
should be measured after lowering V to GND and
IN
IL
BHL
¶
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
#
||
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
Current into an output in the high state when V > V
High-impedance state during power up or power down
O
CC
◊ This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16501, SN74ALVTH16501
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES071D – JUNE 1996 – REVISED JANUARY 1999
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V ± 0.2 V
CC
SN54ALVTH16501 SN74ALVTH16501
MIN MAX MIN MAX
UNIT
MHz
ns
f
t
Clock frequency
Pulse duration
clock
LE high
w
CLK high or low
Data high
Data low
CLK high
CLK low
Data high
Data low
A or B before CLK↑
A or B before LE↓
A or B after CLK↑
t
Setup time
Hold time
ns
ns
su
h
t
CLK high
CLK low
A or B after LE↓
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 2)
= 3.3 V ± 0.3 V
CC
SN54ALVTH16501 SN74ALVTH16501
MIN MAX MIN MAX
UNIT
MHz
ns
f
t
Clock frequency
Pulse duration
clock
LE high
w
CLK high or low
Data high
Data low
CLK high
CLK low
Data high
Data low
A or B before CLK↑
A or B before LE↓
A or B after CLK↑
A or B after LE↓
t
Setup time
Hold time
ns
ns
su
h
t
CLK high
CLK low
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16501, SN74ALVTH16501
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES071D – JUNE 1996 – REVISED JANUARY 1999
switching characteristics over recommended operating free-air temperature range, C = 30 pF,
L
V
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
CC
SN54ALVTH16501 SN74ALVTH16501
MIN MAX MIN MAX
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
f
t
t
t
t
t
t
t
t
t
t
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
A or B
A or B
A or B
A or B
A or B
B or A
ns
ns
ns
ns
LEBA or LEAB
CLKBA or CLKAB
OEBA or OEAB
OEBA or OEAB
switching characteristics over recommended operating free-air temperature range, C = 50 pF,
L
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
CC
SN54ALVTH16501 SN74ALVTH16501
MIN MAX MIN MAX
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
f
t
t
t
t
t
t
t
t
t
t
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
A or B
A or B
A or B
A or B
A or B
B or A
ns
ns
ns
ns
LEBA or LEAB
CLKBA or CLKAB
OEBA or OEAB
OEBA or OEAB
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16501, SN74ALVTH16501
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES071D – JUNE 1996 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16501, SN74ALVTH16501
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES071D – JUNE 1996 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
V
= 3.3 V ± 0.3 V
CC
6 V
S1
Open
500 Ω
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
6 V
PLH PHL
/t
C
= 50 pF
t
L
PLZ PZL
500 Ω
(see Note A)
/t
GND
PHZ PZH
LOAD CIRCUIT
t
w
3 V
0 V
3 V
0 V
1.5 V
Input
1.5 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
3 V
0 V
Data
Input
3 V
0 V
1.5 V
1.5 V
1.5 V
1.5 V
Output Control
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
S1 at 6 V
3 V
V
3 V
0 V
1.5 V
1.5 V
1.5 V
Input
V
V
+ 0.3 V
OL
(see Note B)
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
≈ 0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Copyright 1999, Texas Instruments Incorporated
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