SN74ALVTH16646DGG [TI]
ALVT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-56;
| 型号： | SN74ALVTH16646DGG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ALVT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-56 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总12页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALVTH16646, SN74ALVTH16646
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES072A – JUNE 1996 – REVISED JULY 1996
SN54ALVTH16646 . . . WD PACKAGE
SN74ALVTH16646 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
High-Impedance State During Power Up
and Power Down
1DIR
1CLKAB
1SAB
GND
1OE
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
49
48
5-V I/O Compatible
1CLKBA
1SBA
GND
1B1
High-Drive Outputs (–32 mA/64 mA)
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
1A1
1A2
= 3.3 V, T = 25°C
CC
A
1B2
Auto 3-State Eliminates Bus Current
Loading When Voltage at the Output
V
V
CC
CC
1A3
1A4
1B3
1B4
Exceeds V
CC
Bus-Hold Data Inputs Eliminate the Need
for External Pullup/Pulldown Resistors
1A5 10
47 1B5
GND
1A6
GND
1B6
11
12
46
45
Power Off Disables Inputs/Outputs,
Permitting Live Insertion
1A7 13
1A8 14
2A1 15
2A2 16
44 1B7
43 1B8
42 2B1
41 2B2
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
2A3
2B3
17
40
GND 18
2A4 19
2A5 20
2A6 21
39 GND
38 2B4
37 2B5
36 2B6
description
The ’ALVTH16646 are 16-bit bus transceivers
designed for 2.5-V or 3.3-V V operation, but
V
22
35
V
CC
CC
CC
2A7 23
34 2B7
with the capability to provide a TTL interface to a
5-V system environment.
2A8 24
33 2B8
GND 25
32 GND
31 2SBA
30 2CLKBA
29 2OE
These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the
A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the ′ALVTH16646.
2SAB 26
2CLKAB 27
2DIR 28
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry
used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition
between stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation
mode (OE high), A data can be stored in one register and/or B data can be stored in the other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16646, SN74ALVTH16646
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES072A – JUNE 1996 – REVISED JULY 1996
description (continued)
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V
is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.2 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
The SN74ALVTH16646 is available in TI’s thin very small-outline package (DGV), which provides the same I/O
pin count and functionality of standard Widebus packages in less than half the printed circuit board area.
The SN54ALVTH16646 is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ALVTH16646 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
DATA I/OS
B1 – B8
OPERATION OR FUNCTION
OE
X
X
H
H
L
DIR
X
CLKAB
CLKBA
SAB
X
SBA
X
A1 – A8
Input
†
†
†
=
X
Unspecified
Input
Store A, B unspecified
Store B, A unspecified
Store A and B data
†
X
X
↑
X
X
Unspecified
Input
X
↑
H or L
X
↑
H or L
X
X
X
Input
X
X
X
Input disabled
Output
Input disabled
Input
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
X
L
L
L
X
H or L
X
X
H
Output
Input
L
H
H
X
L
X
Input
Output
L
H or L
X
H
X
Input
Output
†
The data output functions can be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled; i.e., data at
the bus pins is stored on every low-to-high transition of the clock inputs.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16646, SN74ALVTH16646
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES072A – JUNE 1996 – REVISED JULY 1996
DIR CLKAB CLKBA SAB
SBA
L
DIR
H
CLKAB CLKBA SAB
SBA
X
OE
L
OE
L
L
X
X
X
X
X
L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
DIR CLKAB CLKBA SAB
SBA
X
DIR
L
CLKAB CLKBA SAB
SBA
H
OE
X
OE
L
X
H or L
X
X
H
X
X
X
X
↑
X
X
X
↑
X
L
H
H or L
X
X
X
H
X
↑
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16646, SN74ALVTH16646
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES072A – JUNE 1996 – REVISED JULY 1996
logic diagram (positive logic)
56
1OE
1
1DIR
55
1CLKBA
54
1SBA
2
1CLKAB
3
1SAB
One of Eight Channels
1D
C1
5
1A1
52
1B1
1D
C1
To Seven Other Channels
29
28
2OE
2DIR
30
31
27
2CLKBA
2SBA
2CLKAB
26
2SAB
One of Eight Channels
1D
C1
15
2A1
42
2B1
1D
C1
To Seven Other Channels
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16646, SN74ALVTH16646
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES072A – JUNE 1996 – REVISED JULY 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state, V (see Note 1) . . . . –0.5 V to 7 V
O
Output current in the low state, I :SN54ALVTH16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ALVTH16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Output current in the high state, I : SN54ALVTH16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –48 mA
O
SN74ALVTH16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . 1 W
A
DGV package . . . . . . . . . . . . . . . . . . 1 W
DL package . . . . . . . . . . . . . . . . . . . 1.4 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation, refertothePackageThermalConsiderationsapplicationnoteintheABTAdvancedBiCMOSTechnologyData
Book.
recommended operating conditions, V
= 2.5 V ± 0.2 V (see Note 3)
CC
SN54ALVTH16646 SN74ALVTH16646
UNIT
MIN
2.3
MAX
MIN
2.3
MAX
V
V
V
V
Supply voltage
2.7
2.7
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
1.7
1.7
0.7
5.5
–6
0.7
5.5
–8
8
V
0
0
V
I
I
High-level output current
Low-level output current
mA
OH
6
I
mA
OL
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 KHz
Outputs enabled
18
24
10
85
∆t/∆v Input transition rise or fall rate
Operating free-air temperature
NOTE 3: Unused control inputs must be held high or low to prevent them from floating.
10
ns/V
T
A
–55
125
–40
°C
recommended operating conditions, V
= 3.3 V ± 0.3 V (see Note 3)
CC
SN54ALVTH16646 SN74ALVTH16646
UNIT
MIN
3
MAX
MIN
3
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
2
2
0.8
5.5
–24
24
0.8
5.5
–32
32
V
0
0
V
I
I
High-level output current
Low-level output current
mA
OH
I
mA
OL
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 KHz
Outputs enabled
48
64
∆t/∆v Input transition rise or fall rate
Operating free-air temperature
10
10
ns/V
T
A
–55
125
–40
85
°C
NOTE 3: Unused control inputs must be held high or low to prevent them from floating.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16646, SN74ALVTH16646
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES072A – JUNE 1996 – REVISED JULY 1996
electrical characteristics over recommended operating free-air temperature range,
V
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 2)
CC
SN54ALVTH16646
SN74ALVTH16646
PARAMETER
TEST CONDITIONS
UNIT
†
TYP
†
TYP
MIN
MAX
MIN
MAX
V
V
V
= 2.3 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 2.3 V to 2.7 V,
I
I
I
I
I
I
I
I
= –100 µA
= – 6 mA
= – 8 mA
= 100 µA
= 6 mA
V
–0.2
CC
1.7
V
CC
–0.2
CC
OH
OH
OH
OL
OL
OL
OL
OL
V
OH
V
V
V
= 2.3 V
CC
CC
1.7
V
= 2.3 V to 2.7 V,
0.2
0.5
0.2
0.5
V
OL
= 8 mA
V
CC
= 2.3 V
= 18 mA
= 24 mA
0.5
0.5
±1
V
V
= 2.7 V,
V = GND
I
±1
10
CC
Control inputs
A or B ports
= 0 or 2.7 V,
V = 2.7 V
I
10
CC
I
I
µA
I
V = V
I
10
10
CC
V
CC
V
CC
V
CC
= 2.7 V
= 0,
V = 0
I
–5
–5
V or V = 0 to 4.5 V
±100
±100
µA
µA
off
I
O
V = 0.7 V
I
90
75
90
75
= 2.3 V
V = 1.7 V
I
A or B ports
I
I(hold)
‡
V
V
V
= 2.7 V ,
V = 0 to 2.7 V
I
CC
CC
CC
§
I
= 2.3 V,
V
= 3.6 V
µA
µA
EX
O
O
≤ 1.2 V,
V = GND or V
V
= 0.5 V to V
,
CC
¶
I
±100
±100
OZ(PU/PD)
,
OE = don’t care
I
CC
Outputs high
Outputs low
0.04
2.3
0.09
4.5
0.04
2.3
0.09
4.5
V
= 2.7 V,
or GND
CC
I
= 0,
CC
V = V
O
I
mA
CC
I
Outputs
disabled
0.04
0.09
0.04
0.09
C
C
V
V
= 2.5 V,
= 2.5 V,
V = 2.5 V or 0
3
9
3
9
pF
pF
i
CC
I
V
O
= 2.5 V or 0
io
CC
†
‡
§
¶
All typical values are at V
= 2.5 V, T = 25°C.
A
CC
This is the bus-hold maximum dynamic current required to switch the input from one state to another.
Current into an output in the high state when V > V
O
CC
High-impedance state during power up/high-impedance state during power down
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16646, SN74ALVTH16646
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES072A – JUNE 1996 – REVISED JULY 1996
electrical characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 3)
V
CC
SN54ALVTH16646
SN74ALVTH16646
PARAMETER
TEST CONDITIONS
UNIT
†
TYP
†
TYP
MIN
MAX
MIN
MAX
V
V
V
= 3 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 3 V to 3.6 V,
I
I
I
I
I
I
I
I
I
= –100 µA
= – 24 mA
= – 32 mA
= 100 µA
= 16 mA
= 24 mA
= 32 mA
= 48 mA
= 64 mA
V
CC
–0.2
V
CC
–0.2
CC
OH
OH
OH
OL
OL
OL
OL
OL
OL
V
OH
2
V
V
V
= 3 V
CC
CC
2
V
= 3 V to 3.6 V,
0.2
0.5
0.2
0.4
V
OL
V
CC
= 3 V
0.5
0.55
0.55
±1
V
V
= 3.6 V, V = VCC or GND
±1
10
CC
I
Control inputs
A or B ports
= 0 or 3.6 V,
V = 5.5 V
I
10
CC
I
I
V = 5.5 V
I
20
20
µA
V
CC
= 3.6 V
V = V
I CC
10
10
V = 0
I
–5
–5
I
I
I
V
V
= 0,
V or V = 0 to 4.5 V
±100
±100
µA
µA
off
CC
I
O
V = 0.8 V
I
75
75
= 3 V
CC
V = 2 V
I
A or B ports
–75
–75
I(hold)
‡
V
CC
V
CC
V
CC
= 3.6 V ,
V = 0 to 3.6 V
I
±500
±500
§
= 3 V,
V
O
= 5.5 V
125
125
µA
µA
EX
≤ 1.2 V,
V
= 0.5 V to V
,
O
CC
¶
I
±100
±100
OZ(PU/PD)
V = GND or V
I
OE = don’t care
CC,
Outputs high
Outputs low
0.07
3.2
0.09
5
0.07
3.2
0.09
5
V
= 3.6 V,
or GND
CC
I
= 0,
O
CC
V = V
I
mA
mA
CC
I
Outputs
disabled
0.07
0.09
0.2
0.07
0.09
0.2
V
= 3 V to 3.6 V, One input at V –0.6 V,
CC
CC
Other inputs at V
#
∆I
CC
or GND
CC
C
C
V
V
= 3.3 V,
= 3.3 V,
V = 3.3 V or 0
3
9
3
9
pF
pF
i
CC
I
V
O
= 3.3 V or 0
io
CC
†
‡
§
¶
#
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
This is the bus-hold maximum dynamic current required to switch the input from one state to another.
Current into an output in the high state when V > V
O
CC
High-impedance state during power up/high-impedance state during power down
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16646, SN74ALVTH16646
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES072A – JUNE 1996 – REVISED JULY 1996
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 2)
= 2.5 V ± 0.2 V
CC
SN54ALVTH16646 SN74ALVTH16646
UNIT
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency
150
150
MHz
ns
clock
Pulse duration, CLK high or low
1.5
2.5
2.6
0
1.5
2.5
2.6
0
w
Data high
Data low
Data high
Data low
t
Setup time, A or B before CLKAB↑ or CLKBA↑
Hold time, A or B after CLKAB↑ or CLKBA↑
ns
ns
su
h
t
0
0
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 3)
= 3.3 V ± 0.3 V
CC
SN54ALVTH16646 SN74ALVTH16646
UNIT
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency
150
150
MHz
ns
clock
Pulse duration, CLK high or low
1.5
2.1
2.2
0
1.5
2.1
2.2
0
w
Data high
Data low
Data high
Data low
t
Setup time, A or B before CLKAB↑ or CLKBA↑
Hold time, A or B after CLKAB↑ or CLKBA↑
ns
ns
su
h
t
0
0
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16646, SN74ALVTH16646
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES072A – JUNE 1996 – REVISED JULY 1996
switching characteristics over recommended operating free-air temperature range, C = 50 pF,
L
V
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 2)
CC
SN54ALVTH16646
SN74ALVTH16646
†
MAX
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
150
1.2
1.5
1.5
2
MAX
MIN TYP
f
t
150
MHz
max
A or B
B or A
A or B
A or B
A or B
A or B
A or B
A or B
4.5
6.1
6.6
7.1
7.8
7.2
7.9
1.2
1.5
1.5
2
2.3
4.1
5.5
6
CLKBA or CLKAB
3
3.4
3.4
4.2
3.5
4.3
ns
pd
‡
SBA or SAB
t
t
t
t
6.4
7.1
6.5
7.1
ns
ns
ns
ns
OE
OE
en
dis
en
dis
2
2
DIR
DIR
2
2
2
2
†
‡
All typical values are at V
= 2.5 V, T = 25°C.
A
CC
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
switching characteristics over recommended operating free-air temperature range, C = 50 pF,
L
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 3)
CC
SN54ALVTH16646
SN74ALVTH16646
§
MAX
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
150
1
MAX
MIN TYP
f
t
150
MHz
max
A or B
B or A
A or B
A or B
A or B
A or B
A or B
A or B
3.1
3.8
4.4
4.9
6
1
1.8
2.8
3.4
4
CLKBA or CLKAB
2.4
2.4
2.6
3.4
2.6
3.5
ns
pd
‡
1.4
1
1.4
1
SBA or SAB
t
t
t
t
4.4
5.4
4.5
5.4
ns
ns
ns
ns
OE
OE
en
dis
en
dis
1.5
1
1.5
1
DIR
DIR
5
1.5
6
1.5
§
‡
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16646, SN74ALVTH16646
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES072A – JUNE 1996 – REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V
0.2 V
CC
2 × V
CC
Open
GND
TEST
S1
S1
500 Ω
t
Open
pd
/t
From Output
Under Test
t
2 × V
CC
GND
PLZ PZL
/t
t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
t
LOAD CIRCUIT
w
V
CC
V
CC
/2
V
/2
CC
Input
V
CC
Timing
Input
V
/2
0 V
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Data
Input
V
CC
V
CC
/2
V
CC
/2
Output
Control
(low-level
enabling)
0 V
V
CC
/2
V
CC
/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
0 V
t
t
PZL
t
PLZ
V
V
CC
Output
Waveform 1
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
V
OL
+ 0.3 V
S1 at 2 × V
(see Note B)
CC
OL
0 V
t
PHZ
t
PLH
t
PZH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
OH
– 0.3 V
V
CC
/2
Output
V
CC
/2
V
/2
CC
(see Note B)
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 Ω, t 2.5 ns, t 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
en
pd
Figure 2. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH16646, SN74ALVTH16646
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES072A – JUNE 1996 – REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
= 3.3 V ± 0.3 V
V
CC
6 V
TEST
S1
S1
500 Ω
Open
GND
t
Open
6 V
pd
/t
From Output
Under Test
t
PLZ PZL
/t
t
GND
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
1.5 V
Timing Input
Data Input
t
w
t
t
h
su
3 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
Output
Control
1.5 V
1.5 V
t
t
PZL
3 V
0 V
Input
1.5 V
1.5 V
PLZ
1.5 V
Output
Waveform 1
S1 at 6 V
3 V
V
V
+ 0.3 V
– 0.3 V
OL
t
t
V
OL
PHL
PLH
(see Note B)
t
V
V
PHZ
OH
t
PZH
1.5 V
1.5 V
Output
Waveform 2
S1 at GND
Output
V
OH
OL
OH
1.5 V
(see Note B)
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 3. Load Circuit and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright 1998, Texas Instruments Incorporated
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