SN74AS163DG4 [TI]
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS; 同步4位十年和二进制计数器
| 型号： | SN74AS163DG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS |
| 文件： | 总27页 (文件大小：689K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
SN54ALS161B, SN54ALS162B, SN54ALS163B,
Internal Look-Ahead Circuitry for Fast
Counting
SN54AS161, SN54AS163 . . . J PACKAGE
SN74ALS161B, SN74AS161,
Carry Output for n-Bit Cascading
Synchronous Counting
Synchronously Programmable
SN74AS163 . . . D OR N PACKAGE
SN74ALS163B . . . D, DB, OR N PACKAGE
(TOP VIEW)
Package Options Include Plastic
CLR
CLK
A
V
CC
RCO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Small-Outline (D) and Shrink Small-Outline
(DB) Packages, Ceramic Chip Carriers (FK),
Standard Plastic (N) and Ceramic (J) DIPs
Q
A
B
C
D
Q
B
Q
C
description
Q
D
ENT
ENP
GND
These synchronous, presettable, 4-bit decade
and binary counters feature an internal carry
look-ahead circuitry for application in high-speed
counting designs. The SN54ALS162B is a 4-bit
decade counter. The ’ALS161B, ’ALS163B,
’AS161, and ’AS163 devices are 4-bit binary
counters. Synchronous operation is provided by
having all flip-flops clocked simultaneously so that
the outputs change coincidentally with each other
when instructed by the count-enable (ENP, ENT)
inputs and internal gating. This mode of operation
eliminates the output counting spikes normally
associated with asynchronous (ripple-clock)
counters. A buffered clock (CLK) input triggers the
four flip-flops on the rising (positive-going) edge of
the clock input waveform.
LOAD
SN54ALS161B, SN54ALS162B, SN54ALS163B,
SN54AS161, SN54AS163 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
A
B
Q
Q
4
5
6
7
8
A
B
17
16
15
14
NC
C
NC
Q
C
D
Q
D
9 10 11 12 13
These counters are fully programmable; they can
be preset to any number between 0 and 9 or 15.
Because presetting is synchronous, setting up a
low level at the load (LOAD) input disables the
counter and causes the outputs to agree with the
setup data after the next clock pulse, regardless
of the levels of the enable inputs.
NC – No internal connection
The clear function for the ’ALS161B and ’AS161 devices is asynchronous. A low level at the clear (CLR) input
sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD, or enable inputs. The clear
function for the SN54ALS162B, ’ALS163B, and ’AS163 devices is synchronous, and a low level at CLR sets
all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This
synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear
the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this
function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled,
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
description (continued)
produces a high-level pulse while the count is maximum (9 or 15, with Q high). The high-level overflow
A
ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed,
regardless of the level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for
operation over the full military temperature range of –55°C to 125°C. The SN74ALS161B, SN74ALS163B,
SN74AS161, and SN74AS163 are characterized for operation from 0°C to 70°C.
†
logic symbols
’ALS161B AND ’AS161 BINARY COUNTERS
’ALS163B AND ’AS163 BINARY COUNTERS
WITH DIRECT CLEAR
WITH SYNCHRONOUS CLEAR
CTRDIV16
CT=0
CTRDIV16
1
9
1
5CT=0
CLR
CLR
9
M1
M1
M2
G3
LOAD
LOAD
15
15
M2
3CT=15
RCO
3CT=15
RCO
10
10
ENT
G3
ENT
7
2
7
2
ENP
CLK
G4
ENP
CLK
G4
C5/2,3,4+
C5/2,3,4+
3
4
5
6
14
13
12
11
3
4
5
6
14
13
12
11
[1]
[2]
[4]
[8]
Q
A
[1]
[2]
[4]
[8]
Q
A
A
B
C
D
1, 5D
A
B
C
D
1, 5D
Q
B
Q
B
Q
C
Q
C
Q
D
Q
D
SN54ALS162B DECADE COUNTER
WITH SYNCHRONOUS CLEAR
CTRDIV10
5CT=0
1
9
CLR
M1
LOAD
15
M2
3CT=9
RCO
10
ENT
G3
7
2
ENP
CLK
G4
C5/2,3,4+
3
4
5
6
14
13
12
11
Q
A
[1]
[2]
[4]
[8]
A
B
C
D
1, 5D
Q
B
Q
C
Q
D
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, and N packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
logic diagram (positive logic)
SN54ALS162B
9
LOAD
10
7
15
ENT
ENP
RCO
1
CLR
2
CLK
14
C1
1D
Q
A
3
A
13
C1
1D
Q
B
4
B
12
Q
C1
1D
C
5
C
11
C1
1D
Q
D
6
D
Pin numbers shown are for the J package.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
logic diagram (positive logic)
’ALS163B and ’AS163
1
CLR
9
LOAD
10
ENT
15
7
RCO
ENP
2
CLK
14
13
12
C1
1D
Q
Q
Q
A
B
C
3
A
C1
1D
4
B
C1
1D
5
C
11
C1
1D
Q
D
6
D
Pin numbers shown are for the D, DB, J, and N packages.
’ALS161B and ’AS161 synchronous binary counters are similar; however, CLR is asynchronous.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
typical clear, preset, count, and inhibit sequences
SN54ALS162B
The following sequence is illustrated below:
1. Clear outputs to zero (SN54ALS162B is synchronous)
2. Preset to BCD 7
3. Count to 8, 9, 0, 1, 2, and 3
4. Inhibit
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Q
A
Q
Q
Q
B
C
D
Data
Outputs
RCO
7
8
9
0
1
2
3
Count
Inhibit
Sync Preset
Clear
Async
Clear
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
typical clear, preset, count, and inhibit sequences
’ALS161B, ’AS161, ’ALS163B, and ’AS163
The following sequence is illustrated below:
1. Clear outputs to zero (’ALS161B and ’AS161 are asynchronous; ’ALS163B and ’AS163 are
synchronous.)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Q
A
Q
Q
Q
B
C
D
Data
Outputs
RCO
12
13
14
15
0
1
2
Count
Inhibit
Sync Preset
Clear
Async
Clear
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Package thermal impedance, θ (see Note 1): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
SN54ALS161B
SN54ALS162B
SN54ALS163B
SN74ALS161B
SN74ALS163B
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
IH
0.7
–0.4
4
0.8
–0.4
8
V
IL
I
I
mA
mA
°C
OH
OL
T
A
–55
125
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS161B
SN74ALS161B
SN54ALS162B
SN74ALS163B
PARAMETER
TEST CONDITIONS
UNIT
SN54ALS163B
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.5
–1.5
V
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
= –0.4 mA
= 4 mA
V
CC
–2
V
CC
–2
OH
CC
OH
OL
OL
0.25
0.4
0.25
0.35
0.4
0.5
V
OL
V
CC
= 4.5 V
V
= 8 mA
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V
V = 7 V
0.1
20
0.1
mA
µA
I
I
V = 2.7 V
I
20
IH
IL
V = 0.4 V
I
–0.2
–112
21
–0.2
–112
21
mA
mA
mA
§
V
O
= 2.25 V
–20
–30
O
12
12
CC
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, I
.
OS
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
timing requirements over recommended operating conditions (unless otherwise noted) (see
Figure 1)
SN54ALS161B
SN74ALS161B
SN54ALS162B
SN54ALS163B
SN74ALS163B
UNIT
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
22
40
MHz
ns
clock
CLR high or low
’ALS161B
20
20
50
20
25
20
10
20
20
0
12.5
15
15
15
15
15
10
15
10
0
w
CLR low
A, B, C, D
LOAD
’ALS161B
ENP, ENT
t
t
Setup time, before CLK↑
SN54ALS162B, ’ALS163B
’ALS161B
ns
ns
su
CLR inactive
CLR low
SN54ALS162B, ’ALS163B
CLR high
Hold time, all synchronous inputs after CLK↑
h
switching characteristics over recommended operating conditions (unless otherwise noted) (see
Figure 1)
SN54ALS161B SN74ALS161B
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN
22
5
MAX
MIN
40
5
MAX
f
t
t
t
t
t
t
max
PLH
PHL
PLH
PHL
PLH
PHL
34
27
19
25
18
17
27
32
20
20
15
20
13
13
24
23
CLK
CLK
RCO
Any Q
RCO
5
5
4
4
ns
ns
ns
6
6
3
3
ENT
CLR
3
3
Any Q
RCO
8
8
t
PHL
11
11
switching characteristics over recommended operating conditions (unless otherwise noted) (see
Figure 1)
SN54ALS162B
SN54ALS163B
SN74ALS163B
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
22
5
MAX
MIN
40
5
MAX
f
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
25
25
18
25
16
16
20
20
15
20
13
13
CLK
CLK
ENT
RCO
Any Q
RCO
5
5
4
4
ns
ns
6
6
3
3
3
3
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
recommended operating conditions
SN54AS161
SN54AS163
SN74AS161
SN74AS163
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
IH
0.8
–2
0.8
–2
20
70
V
IL
I
I
mA
mA
°C
OH
20
OL
T
A
–55
125
0
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS161
SN54AS163
SN74AS161
SN74AS163
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
V
V
IK
CC
CC
CC
I
= 4.5 V to 5.5 V,
= 4.5 V,
I
= –2 mA
= 20 mA
V
CC
–2
V
CC
–2
OH
OL
OH
OL
I
0.25
0.5
0.3
0.2
0.1
60
0.25
0.5
0.3
0.2
0.1
60
LOAD
ENT
I
I
I
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 7 V
I
mA
µA
I
All others
LOAD
ENT
V = 2.7 V
I
40
40
IH
IL
All others
LOAD
ENT
20
20
–1.5
–1
–1.5
–1
V = 0.4 V
I
mA
All others
–0.5
–112
53
–0.5
–112
53
‡
I
I
V
V
= 5.5 V,
= 5.5 V
V = 2.25 V
O
–30
–30
mA
mA
O
CC
35
35
CC
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
timing requirements over recommended operating conditions (see Figure 1)
SN54AS161
SN54AS163
SN74AS161
SN74AS163
UNIT
MIN
MAX
MIN
MAX
75
f
t
Clock frequency
Pulse duration
65
MHz
ns
clock
CLR high or low
’AS161
7.7
10
10
10
10
10
14
10
2
6.7
8
w
CLR low
A, B, C, D
LOAD
8
8
ENP, ENT
’AS161
8
t
t
Setup time, before CLK↑
ns
ns
su
CLR inactive
CLR low
8
12
9
’AS163
CLR high (inactive)
Hold time, all synchronous inputs after CLK↑
0
h
switching characteristics over recommended operating conditions (see Figure 1)
SN54AS161
SN74AS161
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN
65*
1
MAX
MIN
75
1
MAX
f
t
max
RCO (with LOAD high)
RCO (with LOAD low)
RCO
8.5
17.5
14
8
16.5
12.5
7
CLK
CLK
CLK
PLH
3
3
t
t
t
t
t
2
2
ns
PHL
PLH
PHL
PLH
PHL
1
7.5
14
1
Any Q
RCO
ns
2
2
13
1.5
1
10
1.5
1
9
ns
ns
ENT
CLR
9.5
14
8.5
13
Any Q
RCO
2
2
t
PHL
2
14
2
12.5
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating conditions (see Figure 1)
SN54AS163
SN74AS163
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN
65*
1
MAX
MIN
75
1
MAX
f
t
max
RCO (with LOAD high)
RCO (with LOAD low)
RCO
8.5
17.5
14
8
16.5
12.5
7
CLK
CLK
CLK
PLH
3
3
t
t
t
t
t
2
2
ns
PHL
PLH
PHL
PLH
PHL
1
7.5
14
1
Any Q
RCO
ns
2
2
13
1.5
1
10
1.5
1
9
ns
ENT
9.5
8.5
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
V
CC
S1
500 Ω
Test
Point
500 Ω
From Output
Under Test
Test
Point
From Output
Under Test
Test
Point
From Output
Under Test
C
= 50 pF
C
= 50 pF
L
500 Ω
L
500 Ω
C
= 50 pF
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3 V
0 V
3 V
Timing
High-Level
1.5 V
Input
1.5 V
1.5 V
Pulse
0 V
t
t
w
h
t
su
3 V
3 V
0 V
Data
Input
Low-Level
1.5 V
1.5 V
1.5 V
1.5 V
Pulse
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
Control
(low-level
enabling)
3 V
0 V
1.5 V
1.5 V
3 V
1.5 V
1.5 V
Input
t
t
PLZ
PZL
0 V
PHL
≈3 V
Waveform 1
S1 Closed
(see Note B)
t
t
PLH
PHL
1.5 V
V
OH
In-Phase
Output
V
OL
1.5 V
1.5 V
1.5 V
V
OL
0.3 V
t
PHZ
t
t
t
PZH
PLH
V
OH
Waveform 2
S1 Open
(see Note B)
Out-of-Phase
Output
(see Note C)
V
OH
OL
1.5 V
0.3 V
≈0 V
1.5 V
V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
APPLICATION INFORMATION
n-bit synchronous counters
This application demonstrates how the ripple-mode carry circuit (see Figure 2) and the carry look-ahead circuit
(see Figure 3) can be used to implement a high-speed n-bit counter. The SN54ALS162B counts in BCD. The
’ALS161B, ’AS161, ’ALS163B, and ’AS163 devices count in binary. When additional stages are added, the f
decreases in Figure 2, but remains unchanged in Figure 3.
max
LSB
CTR
LSB
CTR
CLR
LOAD
ENT
ENP
CLK
CLR
LOAD
ENT
ENP
CLK
CT=0
M1
G3
CT=0
M1
G3
Clear (L)
Clear (L)
Count (H)
Disable (L)
Count (H)
Disable (L)
RCO
RCO
3CT=MAX
3CT=MAX
G4
G4
Clock
C5/T,3,4+
C5/T,3,4+
A
B
C
A
B
C
1,5D
1,5D
Q
A
B
Q
A
B
Load (L)
Load (L)
Q
Q
Count (H)
Disable (L)
Q
Q
Q
Q
C
D
C
D
D
D
Clock
CLR
LOAD
ENT
ENP
CLK
CLR
LOAD
ENT
ENP
CLK
CTR
CTR
CT=0
M1
G3
CT=0
M1
G3
RCO
RCO
3CT=MAX
3CT=MAX
G4
G4
C5/T,3,4+
C5/T,3,4+
A
B
C
A
B
C
1,5D
1,5D
Q
Q
Q
Q
A
B
A
B
Q
Q
C
D
C
D
D
D
Q
Q
CLR
LOAD
ENT
ENP
CLK
CLR
LOAD
ENT
ENP
CLK
CTR
CTR
CT=0
M1
G3
CT=0
M1
G3
RCO
RCO
3CT=MAX
3CT=MAX
G4
G4
C5/T,3,4+
C5/T,3,4+
A
B
C
A
B
C
1,5D
1,5D
Q
Q
Q
Q
A
B
A
B
Q
Q
C
D
C
D
D
D
Q
Q
CLR
LOAD
ENT
ENP
CLK
CLR
LOAD
ENT
ENP
CLK
CTR
CTR
CT=0
M1
G3
CT=0
M1
G3
RCO
RCO
3CT=MAX
3CT=MAX
G4
G4
C5/T,3,4+
C5/T,3,4+
A
B
C
A
B
C
1,5D
1,5D
Q
Q
Q
Q
A
B
A
B
Q
Q
C
D
C
D
D
D
Q
Q
To More Significant Stages
) + (ENT to RCO t ) (N – 2) + (ENT t
To More Significant Stages
= 1/(CLK to RCO t ) + (ENP t
f
= 1/(CLK to RCO t
)
su
f
)
su
max
PLH
PLH
max
PLH
Figure 2. Ripple-Mode Carry Circuit
Figure 3. Carry Look-Ahead Circuit
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
83022012A
8302201EA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
FK
J
20
16
16
20
16
16
20
16
20
16
16
16
16
16
16
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
8302201FA
W
FK
J
83022022A
LCCC
CDIP
CFP
POST-PLATE N / A for Pkg Type
8302202EA
A42 SNPB
Call TI
N / A for Pkg Type
Call TI
8302202FA
W
FK
J
JM38510/38001B2A
JM38510/38001BEA
JM38510/38002B2A
JM38510/38002BEA
SN54ALS161BJ
SN54ALS163BJ
SN54AS161J
LCCC
CDIP
LCCC
CDIP
CDIP
CDIP
CDIP
CDIP
SOIC
1
1
1
1
1
1
1
POST-PLATE N / A for Pkg Type
A42 SNPB N / A for Pkg Type
POST-PLATE N / A for Pkg Type
FK
J
A42 SNPB
A42 SNPB
A42 SNPB
A42 SNPB
Call TI
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Call TI
J
J
J
SN54AS163J
J
SN74ALS161BD
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS161BDE4
SN74ALS161BDG4
SN74ALS161BDR
SN74ALS161BDRE4
SN74ALS161BDRG4
SN74ALS161BN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
D
D
D
D
D
N
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74ALS161BN3
SN74ALS161BNE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
16
16
TBD
Call TI
Call TI
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74ALS161BNSR
SN74ALS161BNSRE4
SN74ALS163BD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
NS
NS
D
16
16
16
16
16
16
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SSOP
SSOP
SOIC
SOIC
SOIC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS163BDBR
SN74ALS163BDBRE4
SN74ALS163BDE4
SN74ALS163BDG4
SN74ALS163BDR
DB
DB
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2007
Orderable Device
SN74ALS163BDRE4
SN74ALS163BDRG4
SN74ALS163BN
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
PDIP
D
N
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74ALS163BN3
SN74ALS163BNE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
16
16
TBD
Call TI
Call TI
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74ALS163BNSR
SN74ALS163BNSRE4
SN74AS161D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
NS
NS
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AS161DE4
SN74AS161DG4
SN74AS161DR
SN74AS161DRE4
SN74AS161DRG4
SN74AS161N
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74AS161NE4
SN74AS161NSR
SN74AS161NSRE4
SN74AS163D
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NS
NS
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AS163DE4
SN74AS163DG4
SN74AS163DR
SN74AS163DRE4
SN74AS163DRG4
SN74AS163N
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74AS163NE4
SN74AS163NSR
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74AS163NSRE4
ACTIVE
SO
NS
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54ALS161BFK
SNJ54ALS161BJ
SNJ54ALS161BW
SNJ54ALS163BFK
SNJ54ALS163BJ
SNJ54AS161FK
SNJ54AS161J
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
LCCC
CDIP
CFP
FK
J
20
16
16
20
16
20
16
16
1
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
W
FK
J
LCCC
CDIP
LCCC
CDIP
CDIP
POST-PLATE N / A for Pkg Type
A42 SNPB N / A for Pkg Type
POST-PLATE N / A for Pkg Type
FK
J
A42 SNPB
Call TI
N / A for Pkg Type
Call TI
SNJ54AS163J
J
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
0
(mm)
16
SN74ALS161BDR
SN74ALS161BNSR
SN74ALS163BDBR
SN74ALS163BDR
SN74ALS163BNSR
SN74AS161DR
D
NS
DB
D
16
16
16
16
16
16
16
16
16
FMX
MLA
MLA
FMX
MLA
FMX
MLA
FMX
MLA
6.5
8.2
8.2
6.5
8.2
6.5
8.2
6.5
8.2
10.3
10.5
6.6
12.1
2.5
2
12
12
2
16
16
16
16
16
16
16
16
16
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
330
330
0
16
16
2.5
16
10.3
10.5
10.3
10.5
10.3
10.5
12.1
2.5
NS
D
330
0
16
12
2
16
12.1
2.5
SN74AS161NSR
SN74AS163DR
NS
D
330
0
16
12
2
16
12.1
2.5
SN74AS163NSR
NS
330
16
12
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74ALS161BDR
SN74ALS161BNSR
SN74ALS163BDBR
SN74ALS163BDR
SN74ALS163BNSR
SN74AS161DR
D
NS
DB
D
16
16
16
16
16
16
16
16
16
FMX
MLA
MLA
FMX
MLA
FMX
MLA
FMX
MLA
333.2
333.2
333.2
333.2
333.2
333.2
333.2
333.2
333.2
333.2
333.2
333.2
333.2
333.2
333.2
333.2
333.2
333.2
28.58
28.58
28.58
28.58
28.58
28.58
28.58
28.58
28.58
NS
D
SN74AS161NSR
SN74AS163DR
NS
D
SN74AS163NSR
NS
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2007
Pack Materials-Page 3
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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