SN74AS1843 [TI]
9-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS; 9位总线接口D类锁存器具有三态输出型号: | SN74AS1843 |
厂家: | TEXAS INSTRUMENTS |
描述: | 9-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS |
文件: | 总5页 (文件大小:59K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢀ ꢅꢆ ꢃꢇ
ꢈ ꢉ ꢊꢋ ꢌ ꢍꢊ ꢎꢀ ꢍ ꢋ ꢁꢌ ꢏꢐꢑꢄꢒꢏ ꢍꢓꢉ ꢌ ꢔꢕ ꢏꢍ ꢖꢄꢌ ꢒꢗꢏꢀ ꢍꢘ ꢋꢌ ꢗꢍ ꢇ ꢉ ꢀꢌꢄꢌ ꢏꢍ ꢙ ꢎꢌ ꢕꢎ ꢌꢀ
SDAS127 − APRIL 1987
NT Package
(Top View)
• Center V
and GND Configuration
Provides Minimum Lead Inductance in High
CC
Current Switching Applications
1
24
23
22
21
20
19
18
17
16
15
14
13
5Q
4Q
3Q
2Q
1Q
6Q
7Q
8Q
9Q
PRE
C
2
• 3-State Buffer-Type Outputs Drive
3
Bus-Lines Directly
4
5
• Bus-Structured Pinout
• Provide Extra Bus Driving Latches
Necessary for Wider Address/Data Paths or
Buses With Parity
6
V
CC
7
OC
1D
2D
3D
4D
5D
GND
CLR
9D
8
9
10
11
12
8D
• Buffered Control Inputs to Reduce DC
7D
Loading
6D
• Power-Up High Impedance
• Package Options Include Plastic DIPs. Use
the ′AS843 for Plastic and Ceramic Chip
Carriers and “Small Outline” Package
Options
FUNCTION TABLE
INPUTS
OUTPUT
PRE
CLR
OC
C
D
Q
L
X
L
L
L
L
L
L
X
X
H
H
L
X
X
L
H
L
• Dependable Texas Instruments Quality and
H
H
H
H
Reliability
H
H
H
L
H
X
H
description
Q
O
This 9-bit latch device features three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. It is particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
X
X
H
X
X
Z
†
logic symbol
7
OC
EN
The nine latches are transparent D-type and have
noninverting data (D) inputs.
20
PRE
S2
R
A buffered output control (OC) input can be used
to place the nine outputs in either a normal logic
state (high or low levels) or a high-impedance
state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly.
The high-impedance state and increased drive
provide the capability to drive the bus lines in a
bus-organized system without need for interface
or pullup components.
17
CLR
19
C
C1
1D
8
5
1D
2
1Q
9
4
3
2D
2Q
3Q
10
3D
11
2
4D
4Q
The output control (OC) does not affect the
internal operation of the flip-flops. Old data can be
retained or new data can be entered while the
outputs are off.
12
1
24
23
22
21
5D
5Q
6Q
7Q
8Q
9Q
13
6D
14
7D
15
8D
The SN74AS1843 is characterized for operation
from 0°C to 70°C.
16
9D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12,
ꢕꢐ ꢙ ꢓꢎ ꢒ ꢌꢋ ꢙꢁ ꢓ ꢄꢌꢄ ꢚꢛ ꢜ ꢝꢞ ꢟꢠ ꢡꢚꢝ ꢛ ꢚꢢ ꢣꢤ ꢞ ꢞ ꢥꢛꢡ ꢠꢢ ꢝꢜ
ꢡ
Copyright 1987, Texas Instruments Incorporated
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ꢪ
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
ꢀꢁ ꢂ ꢃꢄ ꢀꢅ ꢆꢃ ꢇ
ꢍ
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SDAS127 − APRIL 1987
logic diagram (positive logic)
7
OC
PRE
CLR
C
20
17
19
S
5
4
3
2
1
C1
1D
R
8
1D
2D
3D
4D
5D
6D
7D
8D
9D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
S
C1
1D
R
9
S
C1
1D
R
10
11
12
13
14
15
16
S
C1
1D
R
S
C1
1D
R
S
24
23
22
21
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
†
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
ꢀꢁ ꢂꢃ ꢄꢀ ꢅꢆ ꢃꢇ
ꢈ ꢉ ꢊꢋ ꢌ ꢍꢊ ꢎꢀ ꢍ ꢋ ꢁꢌ ꢏꢐꢑꢄꢒꢏ ꢍꢓꢉ ꢌ ꢔꢕ ꢏꢍ ꢖꢄꢌ ꢒꢗꢏꢀ ꢍꢘ ꢋꢌ ꢗꢍ ꢇ ꢉ ꢀꢌꢄꢌ ꢏꢍ ꢙ ꢎꢌ ꢕꢎ ꢌꢀ
SDAS127 − APRIL 1987
recommended operating conditions
MIN
4.5
2
NOM MAX
UNIT
V
V
V
V
Supply voltage
5
5.5
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
V
IH
0.8
−24
48
V
IL
I
I
mA
mA
OH
OL
CLR or PRE low
C high
4
4
t
w
Pulse duration, enable C high
ns
t
t
Setup time, data before enable C ↓
Hold time, data after enable C ↓
2.5
2.5
15
14
0
ns
ns
su
h
PRE
CLR
t
Recovery time
ns
r
T
Operating free-air temperature
70
°C
A
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
I = − 18 mA
−1.2
V
IK
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
I
I
I
I
I
I
= − 2 mA
= − 15 mA
= − 24 mA
= 32 mA
= 48 mA
= 2.7 V
V
−2
OH
OH
OH
OL
OL
CC
2.4
V
OH
3.2
V
2
V
V
OL
0.35
0.5
50
I
V
V
µA
µA
OZH
OZL
I
O
O
I
I
I
I
I
= 0.4 V
−50
0.1
20
V = 7 V
I
mA
µA
V = 2.7 V
I
IH
V = 0.4 V
I
−.05
−112
62
mA
mA
IL
‡
V
O
= 2.25 V
−30
O
Output high
37
56
56
I
V
CC
= 5.5 V,
Output low
92
mA
CC
Outputs disabled
92
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
ꢀꢁ ꢂ ꢃꢄ ꢀꢅ ꢆꢃ ꢇ
ꢈ ꢉ ꢊꢋ ꢌ ꢍ ꢊ ꢎꢀ ꢍ ꢋ ꢁꢌ ꢏ ꢐꢑꢄꢒ ꢏꢍ ꢓ ꢉ ꢌꢔ ꢕ ꢏꢍ ꢖꢄꢌ ꢒꢗꢏꢀ ꢍꢘ ꢋꢌ ꢗꢍ ꢇ ꢉ ꢀꢌꢄꢌ ꢏꢍ ꢙꢎ ꢌꢕ ꢎꢌꢀ
SDAS127 − APRIL 1987
switching characteristics over recommended ranges of supply voltage and free-air temperature
(see Note 2)
V
= 4.5 V to 5.5 V,
CC
C
= 50 pF,
= 500 Ω,
= 500 Ω,
L
1
2
R
R
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
T
A
= MIN to MAX
MIN
1
MAX
t
t
t
t
t
t
6.5
9
PLH
PHL
PLH
PHL
PLH
PHL
PZH
ns
ns
D
C
Q
Q
1
2
12
12
10
13
10.5
13.5
8
2
PRE
CLR
Q
Q
2
ns
ns
2
t
2
ns
ns
OC
OC
Q
Q
t
2
PZL
t
1
PHZ
t
1
8
PLZ
NOTE 2: Load circuit and voltage waveforms are shown in Section 1 of the ALS/AS Logic Data Book, 1986.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
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