SN74AS374 [TI]
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS; 八D型边沿触发触发器具有三态输出
| 型号： | SN74AS374 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS |
| 文件： | 总9页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
SN54ALS374A, SN54AS374 . . . J PACKAGE
SN74ALS374A, SN74AS374 . . . DW OR N PACKAGE
(TOP VIEW)
D-Type Flip-Flops in a Single Package With
3-State Bus Driving True Outputs
Full Parallel Access for Loading
Buffered Control Inputs
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
8Q
8D
7D
7Q
6Q
6D
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) DIPs
description
13 5D
12 5Q
These octal D-type edge-triggered flip-flops
feature 3-state outputs designed specifically for
11
GND
CLK
driving
highly
capacitive
or
relatively
low-impedance loads. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
SN54ALS374A, SN54AS374 . . . FK PACKAGE
(TOP VIEW)
On the positive transition of the clock (CLK) input,
the Q outputs are set to the logic levels set up at
the data (D) inputs.
3
2
1
20 19
18
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
4
5
6
7
8
17
16
15
14
A buffered output-enable (OE) input places the
eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and the increased drive
provide the capability to drive bus lines without
interface or pullup components.
9 10 11 12 13
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range
of –55°C to 125°C. The SN74ALS374A and SN74AS374 are characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
H or L
X
X
X
Q
0
H
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
†
logic symbol
logic diagram (positive logic)
1
OE
1
OE
EN
C1
11
11
CLK
CLK
C1
1D
2
1Q
3
3
1D
4
2
5
1D
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
2D
7
6
3D
8
9
4D
13
To Seven Other Channels
12
15
16
19
5D
14
6D
17
7D
18
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Package thermal impedance, θ (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
SN54ALS374A
SN74ALS374A
MIN NOM MAX
UNIT
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
IH
0.7
–1
0.8
–2.6
24
V
IL
I
I
mA
mA
°C
OH
12
OL
T
A
–55
125
0
70
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS374A
SN74ALS374A
PARAMETER
TEST CONDITIONS
UNIT
†
TYP
†
TYP
MIN
MAX
MIN
MAX
V
V
V
= 4.5 V,
I = –18 mA
–1.5
–1.5
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
I
I
= –0.4 mA
= –1 mA
= –2.6 mA
= 12 mA
= 24 mA
= 2.7 V
V
–2
V
CC
–2
CC
OH
OH
OH
OL
OL
CC
2.4
V
OH
3.3
V
V
= 4.5 V
= 4.5 V
CC
CC
2.4
3.2
0.25
0.35
0.25
0.4
0.4
0.5
20
V
OL
V
V
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
V
20
–20
0.1
20
µA
µA
OZH
OZL
I
O
O
= 0.4 V
–20
0.1
20
V = 7 V
I
mA
µA
V = 2.7 V
I
IH
V = 0.4 V
I
–0.2
–112
20
–0.2
–112
19
mA
mA
IL
‡
V
O
= 2.25 V
–20
–30
O
Outputs high
Outputs low
11
19
20
11
19
20
I
V
CC
= 5.5 V
28
28
mA
CC
Outputs disabled
31
31
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
SN54ALS374A SN74ALS374A
UNIT
MIN
MAX
MIN
MAX
f
t
t
t
Clock frequency
Pulse duration
Setup time
30
35
MHz
ns
clock
CLK high or low
Data before CLK↑
Data after CLK↑
16.5
10
4
14
10
0
w
ns
su
h
Hold time
ns
switching characteristics over recommended operating conditions (unless otherwise noted
(see Figure 3)
SN54ALS374A SN74ALS374A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN
30
3
MAX
MIN
35
3
MAX
f
t
t
t
t
t
t
max
PLH
PHL
PZH
PZL
PHZ
PLZ
14
17
18
21
11
19
12
16
17
18
10
18
CLK
Q
Q
Q
5
5
3
3
ns
ns
OE
OE
5
5
1
1
2
2
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
recommended operating conditions
SN54AS374
MIN NOM
SN74AS374
MIN NOM
UNIT
MAX
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
IH
0.7
–12
32
0.8
–15
48
V
IL
I
I
mA
mA
°C
OH
OL
T
A
–55
125
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS374
SN74AS374
PARAMETER
TEST CONDITIONS
UNIT
†
TYP
†
TYP
MIN
MAX
MIN
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
I
I
= –2 mA
= –12 mA
= –15 mA
= 32 mA
= 48 mA
= 2.7 V
V
–2
CC
2.4
V
–2
CC
OH
OH
OH
OL
OL
CC
3.2
V
OH
V
= 4.5 V
= 4.5 V
CC
CC
2.4
3.3
0.29
0.5
V
OL
V
V
0.34
0.5
50
I
I
I
I
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
50
–50
0.1
µA
µA
mA
µA
OZH
OZL
I
O
O
V
= 0.4 V
–50
0.1
V = 7 V
I
V = 2.7 V
I
20
20
IH
OE, CLK
Data
–0.5
–3
–0.5
–2
I
V
= 5.5 V,
= 5.5 V,
V = 0.4 V
mA
mA
IL
CC
CC
I
‡
I
O
V
V
O
= 2.25 V
–30
–112
120
128
128
–30
–112
120
128
128
Outputs high
Outputs low
77
84
84
77
84
84
I
V
CC
= 5.5 V
mA
CC
Outputs disabled
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
SN54AS374
SN74AS374
UNIT
MHz
ns
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
100*
125
clock
CLK high
5.5*
3*
4
3
2
2
w
CLK low
t
t
Setup time
Hold time
Data before CLK↑
Data after CLK↑
3*
ns
ns
su
3*
h
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
switching characteristics over recommended operating conditions (unless otherwise noted)
(see Figure 3)
SN54AS374
SN74AS374
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN
MAX
MIN
125
3
MAX
f
t
t
t
t
t
t
100*
max
PLH
PHL
PZH
PZL
PHZ
PLZ
3
4
2
3
2
2
11
11.5
7
8
9
CLK
Q
Q
Q
4
2
6
ns
ns
OE
OE
11
3
10
6
10
7
2
2
6
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
APPLICATION INFORMATION
Four SN54ALS374A,
SN74ALS374A,
or ’AS374
EN
C
8
8
8
8
’ALS139
X/Y
0
1
2
3
EN
C
A
B
G
1
Output-Enable
Select
2
EN
A
B
G
Input Clock
Select
EN
C
8
8
8
8
Clock
EN
C
8
8
Input
Output
Figure 1. Expandable 4-Word by 8-Bit General File Register
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
APPLICATION INFORMATION
SN54ALS374A,
SN74ALS374A,
or ’AS374
Output Enable 1
Clock 1
EN
C1
1D
Bidirectional
Data Bus 1
Bidirectional
Data Bus 2
SN54ALS374A,
SN74ALS374A,
or ’AS374
EN
C1
Output Enable 2
Clock 2
1D
H
Clock 1
Bus-Exchange
Clock
H
Clock 2
Clock Circuit for Bus Exchange
Figure 2. Bidirectional Bus Driver
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
V
CC
S1
500 Ω
Test
Point
500 Ω
From Output
Under Test
From Output
Under Test
Test
Point
From Output
Under Test
Test
Point
C
= 50 pF
L
C
= 50 pF
500 Ω
L
C
= 50 pF
L
500 Ω
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3.5 V
0.3 V
3.5 V
0.3 V
High-Level
Pulse
Timing
Input
1.3 V
1.3 V
1.3 V
t
t
w
h
t
su
3.5 V
0.3 V
3.5 V
0.3 V
Data
Input
Low-Level
Pulse
1.3 V
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
1.3 V
1.3 V
3.5 V
0.3 V
1.3 V
1.3 V
Input
t
t
PLZ
PZL
0.3 V
PHL
≈3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
V
+ 0.3 V
In-Phase
Output
OL
1.3 V
1.3 V
1.3 V
V
V
OL
V
OL
t
t
PHZ
PZH
t
t
PHL
PLH
OH
Out-of-Phase
Output
(see Note C)
V
Waveform 2
S1 Open
(see Note B)
OH
OL
V
– 0.3 V
OH
1.3 V
1.3 V
V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 3. Load Circuits and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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