SN74AS651NT3 [TI]
AS SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDIP24;
| 型号： | SN74AS651NT3 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AS SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDIP24 输入元件 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总34页 (文件大小：910K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
SN54ALS’, SN54AS’ . . . JT PACKAGE
SN74ALS’, SN74AS’ . . . DW OR NT PACKAGE
Bus Transceivers/Registers
Independent Registers and Enables for A
(TOP VIEW)
and B Buses
CLKAB
SAB
OEAB
A1
V
CC
Multiplexed Real-Time and Stored Data
Choice of True or Inverting Data Paths
1
24
23
22
21
20
19
18
17
16
15
14
CLKBA
SBA
OEBA
B1
2
3
Choice of 3-State or Open-Collector
Outputs to A Bus
4
A2
5
A3
B2
6
DEVICE
A OUTPUT
B OUTPUT
LOGIC
A4
B3
7
SN74ALS651A,
’AS651
A5
B4
3-State
3-State
Inverting
8
A6
B5
9
SN54ALS652,
SN74ALS652A,
’AS652
A7
B6
10
11
3-State
3-State
True
A8
B7
GND 12
13 B8
’ALS653
Open Collector
Open Collector
3-State
3-State
Inverting
True
SN74ALS654
SN54ALS’, SN54AS’ . . . FK PACKAGE
(TOP VIEW)
description
These devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select real-time or stored data transfer. The
circuitry used for select control eliminates the
typical decoding glitch that occurs in a multiplexer
during the transition between stored and real-time
data. A low input level selects real-time data, and
a high input level selects stored data. Figure 1
illustrates the four fundamental bus-management
functions that can be performed with the octal bus
transceivers and registers
4
3
2 1 28 27 26
5
6
7
8
9
25 OEBA
A1
A2
A3
NC
A4
A5
A6
24
23
22
21
20
19
B1
B2
NC
B3
B4
B5
10
11
12 13 14 15 16 17 18
NC – No internal connection
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When
SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type
flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input.
When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains
at its last state.
The -1 versions of the SN74ALS651A and SN74ALS652A are identical to the standard versions except that the
recommended maximum I
SN54ALS652, SN54ALS653, SN74ALS653, and SN74ALS654.
for the -1 versions is increased to 48 mA. There are no -1 versions of the
OL
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
SN74ALS651ANT
SN74ALS652ANT
SN74ALS653NT
SN74ALS654NT
SN74AS651NT
SN74ALS651ANT
SN74ALS652ANT
SN74ALS653NT
SN74ALS654NT
SN74AS651NT
SN74AS652NT
PDIP – NT
Tube
SN74AS652NT
Tube
SN74ALS651ADW
SN74ALS651ADWR
SN74ALS652ADW
SN74ALS652ADWR
SN74ALS653DW
SN74ALS653DWR
SN74ALS654DW
SN74ALS654DWR
SN74AS651DW
SN74AS651DWR
SN74AS652DW
SN74AS652DWR
SNJ54ALS652JT
SNJ54ALS653JT
SNJ54AS651JT
SNJ54AS652JT
SNJ54ALS652FK
SNJ54ALS653FK
SNJ54AS651FK
SNJ54AS652FK
ALS651A
ALS652A
ALS653
ALS654
AS651
Tape and reel
Tube
0°C to 70°C
Tape and reel
Tube
Tape and reel
Tube
SOIC – DW
Tape and reel
Tube
Tape and reel
Tube
AS652
Tape and reel
SNJ54ALS652JT
SNJ54ALS653JT
SNJ54AS651JT
SNJ54AS652JT
SNJ54ALS652FK
SNJ54ALS653FK
SNJ54AS651FK
SNJ54AS652FK
CDIP – JT
Tube
Tube
–55°C to 125°C
LCCC – FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
3
21
1
23
2
22
SBA
L
3
21
1
23
2
22
SBA
X
CLKAB CLKBA SAB
CLKAB CLKBA SAB
OEAB OEBA
OEAB OEBA
L
L
X
X
X
H
H
X
X
L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
3
21
23
2
22
3
21
1
23
CLKAB CLKBA SAB
H or L H or L
2
22
SBA
H
1
CLKAB CLKBA SAB
SBA
X
OEAB OEBA
OEAB OEBA
X
L
L
H
X
H
X
↑
X
X
X
H
L
H
↑
X
X
X
↑
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Pin numbers shown are for the DW, JT, and NT packages.
Figure 1. Bus-Management Functions
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
Function Tables
SN54ALS653, SN54AS651,
SN74ALS651A, SN74ALS653, SN74AS651
†
INPUTS
CLKAB
DATA I/O
OPERATION OR FUNCTION
OEAB
OEBA
CLKBA
SAB
X
SBA
X
A1–A8
Input
B1–B8
Input
L
L
H
H
H
H
X
L
H or L
H or L
Isolation
↑
↑
X
X
Input
Input
Store A and B data
‡
X
H
L
↑
H or L
X
X
Input
Unspecified
Output
Input
Store A, hold B
‡
X
↑
↑
X
Input
Store A in both registers
Hold A, store B
‡
H or L
↑
X
X
Unspecified
Output
Output
Output
Input
‡
X
L
↑
X
↑
X
X
X
X
L
Input
Store B in both registers
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
L
L
Input
L
L
X
H or L
X
H
X
X
Input
H
H
H
H
X
Output
Output
H or L
X
H
Input
Stored A data to B bus and
stored B data to A bus
H
L
H or L
H or L
H
H
Output
Output
†
‡
The data output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data input functions always are
enabled; i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.
Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered to load both registers.
SN54ALS652, SN54AS652,
SN74ALS652A, SN74ALS654, SN74AS652
†
INPUTS
CLKAB
DATA I/O
OPERATION OR FUNCTION
OEAB
OEBA
CLKBA
SAB
X
SBA
X
A1–A8
Input
B1–B8
Input
L
L
H
H
H
H
X
L
H or L
H or L
Isolation
↑
↑
X
X
Input
Input
Store A and B data
‡
X
H
L
↑
H or L
X
X
Input
Unspecified
Output
Input
Store A, hold B
‡
X
↑
↑
X
Input
Store A in both registers
Hold A, store B
‡
H or L
↑
X
X
Unspecified
Output
Output
Output
Input
‡
X
L
↑
X
↑
X
X
X
X
L
Input
Store B in both registers
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
L
L
Input
L
L
X
H or L
X
H
X
X
Input
H
H
H
H
X
Output
Output
H or L
X
H
Input
Stored A data to B bus and
stored B data to A bus
H
L
H or L
H or L
H
H
Output
Output
†
‡
The data output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data input functions always are
enabled; i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.
Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered to load both registers.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
†
logic symbols
SN54AS651,
SN74ALS651A, SN74AS651
SN54ALS652, SN54AS652,
SN74ALS652A, SN74AS652
21
21
OEBA
3
OEBA
EN1 [BA]
EN2 [AB]
EN1 [BA]
EN2 [AB]
3
OEAB
23
OEAB
CLKBA
SBA
23
22
1
CLKBA
22
C4
G5
C4
G5
SBA
1
CLKAB
2
CLKAB
SAB
C6
C6
2
SAB
G7
G7
20
20
4D
2
B1
4D
2
B1
5
5
5
5
≥1
≥1
4
4
A1
A1
1
1
1
1
6D
7
7
≥1
6D
7
7
≥1
1
1
5
A2
6
19
18
17
16
15
14
13
5
19
18
17
16
15
14
13
B2
B3
B4
B5
B6
B7
B8
A2
A3
A4
A5
A6
A7
A8
B2
B3
B4
B5
B6
B7
B8
6
A3
7
7
A4
8
8
A5
9
9
A6
10
A7
11
10
11
A8
SN54ALS653, SN74ALS653
SN74ALS654
21
21
OEBA
3
OEBA
EN1 [BA]
EN2 [AB]
EN1 [BA]
EN2 [AB]
3
OEAB
23
OEAB
CLKBA
SBA
23
22
1
CLKBA
22
C4
G5
C4
G5
SBA
1
CLKAB
2
CLKAB
SAB
C6
C6
2
SAB
G7
G7
20
20
4D
2
B1
4D
B1
5
5
5
5
≥1
≥1
4
4
A1
A1
1
1
1
1
6D
7
7
≥1
6D
7
7
≥1
2
1
1
5
A2
6
19
18
17
16
15
14
13
5
19
18
17
16
15
14
13
B2
B3
B4
B5
B6
B7
B8
A2
A3
A4
A5
A6
A7
A8
B2
B3
B4
B5
B6
B7
B8
6
A3
7
7
A4
8
8
A5
9
9
A6
10
A7
11
10
11
A8
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
logic diagrams (positive logic)
21
OEBA
SN54ALS653, SN54AS651,
SN74ALS651A, SN74ALS653, SN74AS651
3
OEAB
CLKBA
SBA
23
22
1
CLKAB
2
SAB
One of Eight Channels
1D
C1
4
A1
20
B1
1D
C1
To Seven Other Channels
SN54ALS652, SN54AS652,
21
OEBA
SN74ALS652A, SN74ALS654, SN74AS652
3
OEAB
CLKBA
SBA
23
22
1
CLKAB
2
SAB
One of Eight Channels
1D
C1
4
A1
20
B1
1D
C1
To Seven Other Channels
Pin numbers shown are for the DW, JT, and NT packages.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V : Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Package thermal impedance, θ (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
JA
NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
SN74ALS651A
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
IH
0.8
–15
24
V
IL
I
I
f
t
mA
OH
Low-level output current
Clock frequency
mA
MHz
ns
OL
clock
w
‡
48
0
12.5
12.5
10
40
CLKBA or CLKAB high
CLKBA or CLKAB low
A or B
Pulse duration
t
t
Setup time before CLKAB↑ or CLKBA↑
Hold time after CLKAB↑ or CLKBA↑
Operating free-air temperature
ns
ns
°C
su
A or B
0
h
T
A
0
70
‡
Applies only to the SN74ALS651A-1 and only if V
CC
is maintained between 4.75 V and 5.25 V
recommended operating conditions
SN54ALS652
MIN NOM MAX
SN74ALS652A
UNIT
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
IH
0.7
–12
12
0.8
–15
24
V
IL
I
I
f
t
mA
OH
Low-level output current
Clock frequency
mA
MHz
ns
OL
clock
w
‡
48
0
14.5
14.5
15
35
0
12.5
12.5
10
40
CLKBA or CLKAB high
CLKBA or CLKAB low
A or B
Pulse duration
t
t
Setup time before CLKAB↑ or CLKBA↑
Hold time after CLKAB↑ or CLKBA↑
Operating free-air temperature
ns
ns
°C
su
A or B
5
0
h
T
A
–55
125
0
70
‡
Applies only to the SN74ALS652A-1 and only if V
CC
is maintained between 4.75 V and 5.25 V
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74ALS651A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
I
I
I
= –0.4 mA
= –3 mA
V
–2
CC
OH
OH
OH
OL
OL
OL
CC
2.4
2
3.2
V
V
OH
V
= 4.5 V
= 4.5 V
CC
CC
= –15 mA
= 12 mA
0.25
0.35
0.35
0.4
0.5
0.5
0.1
0.1
20
V
V
OL
= 24 mA
V
CC
V
CC
V
CC
= 4.75 V,
= 5.5 V,
= 5.5 V,
= 48 mA (-1 versions)
Control inputs
V = 7 V
I
I
I
mA
I
A or B ports
V = 5.5 V
I
Control inputs
V
CC
= 5.5 V,
V = 2.7 V
I
µA
IH
‡
20
A or B ports
Control inputs
–0.2
–0.2
–112
68
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 0.4 V
mA
mA
IL
CC
I
‡
A or B ports
§
V
O
= 2.25 V
–30
CC
O
Outputs high
Outputs low
42
52
52
I
V
CC
= 5.5 V
82
mA
CC
Outputs disabled
82
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
For I/O ports, the parameters I and I include the off-state output current.
IH
IL
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, I
.
OS
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS652
SN74ALS652A
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
I
I
I
I
= –0.4 mA
= –3 mA
V
–2
V
–2
CC
OH
OH
OH
OH
OL
OL
OL
CC
2.4
CC
2.4
3.2
3.2
V
V
OH
V
CC
= 4.5 V
= –12 mA
2
= –15 mA
2
= 12 mA
0.25
0.4
0.25
0.35
0.35
0.4
0.5
0.5
0.1
0.1
20
V
CC
= 4.5 V
V
OL
= 24 mA
V
CC
V
CC
V
CC
= 4.75 V,
= 5.5 V,
= 5.5 V,
= 48 mA (-1 versions)
Control inputs
A or B ports
V = 7 V
I
0.1
0.1
I
I
mA
I
V = 5.5 V
I
Control inputs
20
V
CC
= 5.5 V,
V = 2.7 V
I
µA
IH
IL
‡
20
20
A or B ports
Control inputs
–0.2
–0.2
–112
76
–0.2
–0.2
–112
76
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 0.4 V
I
mA
mA
CC
‡
A or B ports
§
V
O
= 2.25 V
–20
–30
O
CC
Outputs high
Outputs low
47
55
55
47
55
55
I
V
CC
= 5.5 V
88
88
mA
CC
Outputs disabled
88
88
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
For I/O ports, the parameters I and I include the off-state output current.
IH
IL
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, I
.
OS
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
switching characteristics (see Figure 2)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
R1 = 500 Ω,
R2 = 500 Ω,
T
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
†
= MIN to MAX
SN74ALS651A
MIN
40
8
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
32
17
18
10
38
21
25
21
20
18
9
CLKBA or CLKAB
A or B
A or B
B or A
A or B
A or B
A
5
2
ns
ns
ns
ns
ns
ns
ns
2
‡
8
SBA or SAB
(with A or B high)
6
‡
8
SBA or SAB
(with A or B low)
7
3
OEBA
5
2
A
OEBA
OEAB
3
12
22
21
12
14
3
B
6
2
OEAB
B
2
†
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
switching characteristics (see Figure 2)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
R1 = 500 Ω,
R2 = 500 Ω,
T
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
†
= MIN to MAX
SN54ALS652 SN74ALS652A
MIN
35
10
5
MAX
MIN
40
8
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
35
20
20
15
40
23
30
24
20
22
12
20
25
21
12
21
30
17
18
12
35
20
25
20
17
18
10
16
22
18
10
16
CLKBA or CLKAB
A or B
A or B
B or A
A or B
A or B
A
5
5
4
ns
ns
ns
ns
ns
ns
ns
3
3
15
6
8
‡
SBA or SAB
(with A or B high)
6
8
8
‡
SBA or SAB
(with A or B low)
5
5
3
3
OEBA
5
5
1
1
A
OEBA
OEAB
2
2
8
3
B
6
5
1
1
OEAB
B
2
2
†
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V : Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Package thermal impedance, θ (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
JA
NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
SN54ALS653
SN74ALS653
MIN NOM MAX
UNIT
MIN NOM
MAX
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output voltage
High-level output current
Low-level output current
Clock frequency
IH
0.7
5.5
–12
12
0.8
5.5
–15
24
V
IL
A ports
B ports
V
OH
I
I
f
mA
mA
MHz
OH
OL
0
20
25
0
14.5
14.5
10
35
clock
CLKBA or CLKAB high
CLKBA or CLKAB low
A or B
t
w
Pulse duration
ns
20
t
t
Setup time before CLKAB↑ or CLKBA↑
Hold time after CLKAB↑ or CLKBA↑
Operating free-air temperature
15
ns
ns
°C
su
A or B
5
0
h
T
A
–55
125
0
70
recommended operating conditions
SN74ALS654
UNIT
MIN NOM
MAX
V
V
V
V
Supply voltage
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output voltage
High-level output current
Low-level output current
Clock frequency
IH
0.8
5.5
–15
24
V
IL
A ports
B ports
V
OH
I
I
f
mA
mA
MHz
OH
OL
0
14.5
14.5
10
35
clock
CLKBA or CLKAB high
CLKBA or CLKAB low
A or B
t
w
Pulse duration
ns
t
t
Setup time before CLKAB↑ or CLKBA↑
Hold time after CLKAB↑ or CLKBA↑
Operating free-air temperature
ns
ns
°C
su
A or B
0
h
T
A
0
70
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS653
SN74ALS653
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
I
I
I
= –0.4 mA
= –3 mA
= –12 mA
= –15 mA
= 12 mA
V
–2
V
–2
CC
OH
OH
OH
OH
OL
OL
CC
2.4
CC
2.4
3.2
3.2
B ports
V
OH
V
CC
= 4.5 V
2
2
0.25
0.4
0.25
0.35
0.4
0.5
0.1
0.1
20
V
OL
V
CC
= 4.5 V
V
= 24 mA
Control inputs
A or B ports
V
V
= 5.5 V,
= 5.5 V,
V = 7 V
I
0.1
0.1
CC
I
I
I
mA
µA
mA
I
V = 5.5 V
I
CC
Control inputs
20
V
= 5.5 V,
= 5.5 V,
V = 2.7 V
I
IH
CC
CC
‡
20
20
A or B ports
Control inputs
–0.2
–0.2
0.1
–0.2
–0.2
0.1
–112
76
V
V = 0.4 V
I
IL
‡
A or B ports
I
I
A ports
B ports
V
V
= 4.5 V,
= 5.5 V,
V
V
= 5.5 V
mA
mA
OH
CC
OH
= 2.25 V
§
–20
–112
76
–30
CC
O
O
Outputs high
Outputs low
47
55
55
47
55
55
I
V
CC
= 5.5 V
88
88
mA
CC
Outputs disabled
88
88
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
For I/O ports, the parameters I and I include the off-state output current.
IH
IL
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, I
.
OS
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74ALS654
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
I
I
= –0.4 mA
= –3 mA
= –15 mA
= 12 mA
V
–2
CC
OH
OH
OH
OL
OL
CC
2.4
B ports
3.2
V
OH
V
= 4.5 V
= 4.5 V
CC
CC
2
0.25
0.35
0.4
0.5
0.1
0.1
20
V
OL
V
V
= 24 mA
Control inputs
A or B ports
V
V
= 5.5 V,
= 5.5 V,
V = 7 V
I
CC
I
I
I
mA
µA
mA
I
V = 5.5 V
I
CC
Control inputs
V
= 5.5 V,
= 5.5 V,
V = 2.7 V
I
IH
CC
CC
‡
A or B ports
20
Control inputs
–0.2
–0.2
0.1
–112
76
V
V = 0.4 V
I
IL
‡
A or B ports
A ports
I
I
V
V
= 4.5 V,
= 5.5 V,
V
V
= 5.5 V
mA
mA
OH
CC
OH
= 2.25 V
O
§
B ports
–30
O
CC
Outputs high
Outputs low
47
55
55
I
V
CC
= 5.5 V
88
mA
CC
Outputs disabled
88
†
‡
§
All typical values are at V
For I/O ports, the parameters I and I include the off-state output current.
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, I
= 5 V, T = 25°C.
A
IH IL
CC
.
OS
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
switching characteristics (see Figure 2)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
= 680 Ω (A outputs),
CC
L
L
FROM
(INPUT)
TO
(OUTPUT)
R1 = R2 = 500 Ω (B outputs),
T
A
PARAMETER
UNIT
†
= MIN to MAX
SN54ALS653 SN74ALS653
MIN
25
16
6
MAX
MIN
35
16
6
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
71
24
35
20
20
18
63
18
68
27
68
27
30
25
40
25
35
27
25
25
16
21
64
22
30
17
18
15
56
15
62
25
62
25
35
22
25
22
30
24
22
22
14
16
CLKBA
A
B
B
A
A
A
B
B
A
B
B
10
5
10
5
CLKAB
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
A
B
1.5
8
2
12
2
2
‡
12
5
19
5
SBA
(with B high)
‡
12
5
19
5
SBA
(with B low)
‡
8
15
6
SAB
(with A high)
6
‡
SAB
12
6
8
(with A low)
6
6
6
OEBA
6
6
7
8
OEAB
OEAB
6
6
1
1
2
2
†
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
switching characteristics (see Figure 2)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
= 680 Ω (A outputs),
CC
L
L
FROM
(INPUT)
TO
(OUTPUT)
R1 = R2 = 500 Ω (B outputs),
T
A
PARAMETER
UNIT
†
= MIN to MAX
SN74ALS654
MIN
35
16
6
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
64
22
30
17
18
15
56
21
62
25
62
25
35
22
25
22
30
24
22
22
14
16
CLKBA
A
B
B
A
A
A
B
B
A
B
B
10
5
CLKAB
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
A
B
2
12
2
‡
19
5
SBA
(with B low)
‡
19
5
SBA
(with B high)
‡
15
6
SAB
(with A low)
‡
SAB
8
(with A high)
6
6
OEBA
6
6
OEAB
OEAB
6
1
2
†
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V : Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Package thermal impedance, θ (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
JA
NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
SN54AS651
SN54AS652
SN74AS651
SN74AS652
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
IH
0.8
–12
32
0.8
–15
48
V
IL
I
I
f
mA
mA
MHz
OH
OL
clock
0*
6*
75*
0
5
6
6
0
0
90
CLKBA or CLKAB high
CLKBA or CLKAB low
A or B
t
w
Pulse duration
ns
7*
t
t
Setup time before CLKAB↑ or CLKBA↑
Hold time after CLKAB↑ or CLKBA
Operating free-air temperature
7*
ns
ns
°C
su
A or B
0*
h
T
A
–55
125
70
* On products compliant to MIL-PRF-38535, this parameter is based on characterized data but is not production tested.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS651
SN54AS652
SN74AS651
SN74AS652
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
I
I
I
= –2 mA
= –3 mA
= –12 mA
= –15 mA
= 32 mA
= 48 mA
V
–2
V
–2
CC
OH
OH
OH
OH
OL
OL
CC
2.4
CC
2.4
3.2
3.2
V
OH
V
CC
= 4.5 V
2
2
0.25
0.5
V
OL
V
CC
= 4.5 V
V
0.35
0.5
0.1
Control inputs
A or B ports
V
V
= 5.5 V,
= 5.5 V,
V = 7 V
I
0.1
0.1
CC
I
I
mA
µA
V = 5.5 V
I
0.1
CC
Control inputs
20
20
I
V
CC
= 5.5 V,
V = 2.7 V
I
IH
IL
‡
70
70
A or B ports
Control input
–0.5
–0.75
–112
185
195
195
195
211
–0.5
–0.75
–112
185
195
195
195
211
211
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 0.4 V
I
mA
mA
CC
‡
A or B ports
§
V
O
= 2.25 V
–30
–30
CC
O
Outputs high
Outputs low
110
120
130
120
130
130
110
120
130
120
130
130
′AS651
′AS652
V
V
= 5.5 V
= 5.5 V
CC
Outputs disabled
Outputs high
Outputs low
I
mA
CC
CC
Outputs disabled
211
†
‡
§
All typical values are at V
For I/O ports, the parameters I and I include the off-state output current.
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, I
= 5 V, T = 25 °C.
A
IH IL
CC
.
OS
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
switching characteristics (see Figure 2)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
R1 = 500 Ω,
R2 = 500 Ω,
T
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
†
= MIN to MAX
SN54AS651
SN74AS651
MIN
75*
2
MAX
MIN
90
2
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
11
10
12
8
8.5
9
CLKBA or CLKAB
A or B
A or B
2
2
2
2
8
B or A
ns
ns
ns
ns
ns
ns
1
1
7
2
15
11
11
18
10
10
12
20
11
12
2
11
9
‡
A or B
SBA or SAB
2
2
2
2
10
16
9
A
A
B
B
OEBA
OEBA
OEAB
OEAB
3
3
2
2
2
2
9
3
3
11
16
10
11
3
3
2
2
2
2
* On products compliant to MIL-PRF-38535, this parameter is based on characterized data but is not production tested.
†
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
switching characteristics (see Figure 2)
V
= 4.5 V TO 5.5 V,
CC
C
= 50 PF,
L
R1 = 500 Ω,
R2 = 500 Ω,
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
†
T
= MIN TO MAX
A
SN54AS652
SN74AS652
MIN
75*
2
MAX
TYP
90
2
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
11
10
12
8
8.5
9
CLKBA or CLKAB
A or B
A or B
2
2
2
2
9
B or A
ns
ns
ns
ns
ns
ns
1
1
7
2
15
11
11
18
10
10
12
20
11
12
2
11
9
‡
A or B
SBA or SAB
2
2
2
2
10
16
9
A
A
B
B
OEBA
OEBA
OEAB
OEAB
3
3
2
2
2
2
9
3
3
11
16
10
11
3
3
2
2
2
2
* On products compliant to MIL-PRF-38535, this parameter is based on characterized data but is not production tested.
†
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066G – DECEMBER 1983 – REVISED DECEMBER 2000
PARAMETER MEASUREMENT INFORMATION
7 V
V
CC
SWITCH POSITION TABLE
Open
S1
TEST
S1
R
L
t
t
t
Open
Open
Open
Closed
Open
Closed
PLH
PHL
PZH
R1 = 500 Ω
From Output
Under Test
Test Point
From Output
Under Test
Test Point
R2 = 500 Ω
t
PZL
PHZ
C = 50 pF
L
(see Note A)
C
= 50 pF
L
t
(see Note A)
t
PLZ
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
3.5 V
1.3 V
1.3 V
High-Level
Timing
Input
1.3 V
Pulse
0.3 V
t
0.3 V
3.5 V
w
t
h
t
su
3.5 V
0.3 V
Data
Input
Low-Level
Pulse
1.3 V
1.3 V
1.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3.5 V
Output
Control
1.3 V
1.3 V
0.3 V
3.5 V
3.5 V
t
Input
1.3 V
1.3 V
PZL
t
PLZ
0.3 V
PHL
t
t
PLH
Waveform 1
S1 Closed
(see Note B)
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
V
OL
0.3 V
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
1.3 V
1.3 V
0.3 V
0 V
V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
o
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuits and Voltage Waveforms
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-88673013A
ACTIVE
LCCC
FK
28
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
88673013A
SNJ54ALS
652FK
5962-8867301KA
5962-8867301LA
OBSOLETE
ACTIVE
CFP
W
24
24
TBD
TBD
Call TI
A42
Call TI
-55 to 125
-55 to 125
CDIP
JT
1
1
N / A for Pkg Type
5962-8867301LA
SNJ54ALS652JT
5962-88687013A
ACTIVE
LCCC
FK
28
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
88687013A
SNJ54AS
652FK
5962-8868701KA
5962-8868701LA
ACTIVE
ACTIVE
CFP
W
24
24
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-8868701KA
SNJ54AS652W
CDIP
JT
5962-8868701LA
SNJ54AS652JT
5962-8875301KA
5962-89687013A
OBSOLETE
ACTIVE
CFP
W
24
28
TBD
TBD
Call TI
Call TI
-55 to 125
-55 to 125
LCCC
FK
1
POST-PLATE
N / A for Pkg Type
5962-
89687013A
SNJ54ALS
653FK
5962-8968701KA
5962-8968701LA
SN54ALS652JT
ACTIVE
ACTIVE
ACTIVE
CFP
CDIP
CDIP
W
JT
JT
24
24
24
1
1
1
TBD
TBD
TBD
A42
A42
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
5962-8968701KA
SNJ54ALS653W
5962-8968701LA
SNJ54ALS653JT
SN54ALS652JT
SN54AS651JT
SN54AS652JT
OBSOLETE
ACTIVE
CDIP
CDIP
JT
JT
24
24
TBD
TBD
Call TI
A42
Call TI
-55 to 125
-55 to 125
1
N / A for Pkg Type
SN54AS652JT
SN74ALS651A-1DW
SN74ALS651A-1DWR
SN74ALS651A-1NT
SN74ALS651ANT
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
SOIC
SOIC
PDIP
PDIP
DW
DW
NT
24
24
24
24
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
0 to 70
0 to 70
0 to 70
0 to 70
Call TI
Call TI
NT
15
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74ALS651ANT
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SN74ALS651ANTE4
SN74ALS652A-1DW
SN74ALS652A-1DWE4
SN74ALS652A-1DWG4
SN74ALS652A-1NT
SN74ALS652A-1NTE4
SN74ALS652ADW
ACTIVE
PDIP
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
NT
24
24
24
24
24
24
24
24
24
24
24
24
24
24
15
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
SN74ALS651ANT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DW
DW
DW
NT
25
25
Green (RoHS
& no Sb/Br)
ALS652A-1
ALS652A-1
ALS652A-1
74ALS652A-1NT
74ALS652A-1NT
ALS652A
Green (RoHS
& no Sb/Br)
25
Green (RoHS
& no Sb/Br)
15
Pb-Free
(RoHS)
NT
15
Pb-Free
(RoHS)
N / A for Pkg Type
DW
DW
DW
DW
DW
DW
NT
25
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
SN74ALS652ADWE4
SN74ALS652ADWG4
SN74ALS652ADWR
SN74ALS652ADWRE4
SN74ALS652ADWRG4
SN74ALS652ANT
25
Green (RoHS
& no Sb/Br)
ALS652A
25
Green (RoHS
& no Sb/Br)
ALS652A
2000
2000
2000
15
Green (RoHS
& no Sb/Br)
ALS652A
Green (RoHS
& no Sb/Br)
ALS652A
Green (RoHS
& no Sb/Br)
ALS652A
Pb-Free
(RoHS)
SN74ALS652ANT
SN74ALS652ANT
SN74ALS652ANTE4
NT
15
Pb-Free
(RoHS)
N / A for Pkg Type
SN74ALS653-1DW
SN74ALS653-1NT
SN74ALS653DW
OBSOLETE
OBSOLETE
ACTIVE
SOIC
PDIP
SOIC
DW
NT
24
24
24
TBD
TBD
Call TI
Call TI
Call TI
Call TI
0 to 70
0 to 70
0 to 70
DW
25
25
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ALS653
ALS653
ALS653
SN74ALS653DWE4
SN74ALS653DWG4
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
24
24
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
Green (RoHS
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SN74ALS653DWR
SN74ALS653DWRE4
SN74ALS653DWRG4
SN74ALS653NT
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
DW
24
24
24
24
24
24
24
24
24
24
24
24
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
ALS653
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DW
DW
NT
2000
2000
15
Green (RoHS
& no Sb/Br)
ALS653
Green (RoHS
& no Sb/Br)
ALS653
Pb-Free
(RoHS)
SN74ALS653NT
SN74ALS653NT
ALS654
SN74ALS653NTE4
SN74ALS654DW
NT
15
Pb-Free
(RoHS)
N / A for Pkg Type
DW
DW
DW
DW
DW
DW
NT
25
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
SN74ALS654DWE4
SN74ALS654DWG4
SN74ALS654DWR
SN74ALS654DWRE4
SN74ALS654DWRG4
SN74ALS654NT
25
Green (RoHS
& no Sb/Br)
ALS654
25
Green (RoHS
& no Sb/Br)
ALS654
2000
2000
2000
15
Green (RoHS
& no Sb/Br)
ALS654
Green (RoHS
& no Sb/Br)
ALS654
Green (RoHS
& no Sb/Br)
ALS654
Pb-Free
(RoHS)
SN74ALS654NT
SN74ALS654NT
SN74ALS654NTE4
NT
15
Pb-Free
(RoHS)
N / A for Pkg Type
SN74AS651DW
SN74AS651DWR
SN74AS651NT
SN74AS652DW
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
SOIC
SOIC
PDIP
SOIC
DW
DW
NT
24
24
24
24
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
0 to 70
0 to 70
0 to 70
0 to 70
Call TI
Call TI
DW
25
25
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AS652
AS652
AS652
SN74AS652DWE4
SN74AS652DWG4
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
24
24
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
Green (RoHS
& no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SN74AS652NT
SN74AS652NTE4
SNJ54ALS652FK
ACTIVE
PDIP
PDIP
LCCC
NT
24
24
28
15
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
POST-PLATE
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
SN74AS652NT
ACTIVE
ACTIVE
NT
FK
15
1
Pb-Free
(RoHS)
0 to 70
SN74AS652NT
TBD
-55 to 125
5962-
88673013A
SNJ54ALS
652FK
SNJ54ALS652JT
ACTIVE
CDIP
JT
24
1
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8867301LA
SNJ54ALS652JT
SNJ54ALS652W
SNJ54ALS653FK
OBSOLETE
ACTIVE
CFP
W
24
28
TBD
TBD
Call TI
Call TI
-55 to 125
-55 to 125
LCCC
FK
POST-PLATE
N / A for Pkg Type
5962-
89687013A
SNJ54ALS
653FK
SNJ54ALS653JT
SNJ54ALS653W
ACTIVE
ACTIVE
CDIP
CFP
JT
W
24
24
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-8968701LA
SNJ54ALS653JT
5962-8968701KA
SNJ54ALS653W
SNJ54AS651JT
SNJ54AS652FK
OBSOLETE
ACTIVE
CDIP
JT
24
28
TBD
TBD
Call TI
Call TI
-55 to 125
-55 to 125
LCCC
FK
1
POST-PLATE
N / A for Pkg Type
5962-
88687013A
SNJ54AS
652FK
SNJ54AS652JT
SNJ54AS652W
ACTIVE
ACTIVE
CDIP
CFP
JT
W
24
24
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-8868701LA
SNJ54AS652JT
5962-8868701KA
SNJ54AS652W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ALS652, SN54ALS653, SN54AS651, SN54AS652, SN74ALS653, SN74AS651, SN74AS652 :
Catalog: SN74ALS652, SN74ALS653, SN74AS651, SN74AS652
•
Military: SN54ALS653, SN54AS651, SN54AS652
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ALS652ADWR
SN74ALS653DWR
SN74ALS654DWR
SOIC
SOIC
SOIC
DW
DW
DW
24
24
24
2000
2000
2000
330.0
330.0
330.0
24.4
24.4
24.4
10.75 15.7
10.75 15.7
10.75 15.7
2.7
2.7
2.7
12.0
12.0
12.0
24.0
24.0
24.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74ALS652ADWR
SN74ALS653DWR
SN74ALS654DWR
SOIC
SOIC
SOIC
DW
DW
DW
24
24
24
2000
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
45.0
45.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP007 – OCTOBER 1994
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
0.375 (9,53)
0.340 (8,64)
Base and Seating Plane
0.006 (0,15)
0.004 (0,10)
0.045 (1,14)
0.026 (0,66)
0.090 (2,29)
0.045 (1,14)
0.395 (10,03)
0.360 (9,14)
0.360 (9,14)
0.240 (6,10)
0.360 (9,14)
0.240 (6,10)
0.019 (0,48)
0.015 (0,38)
1
24
0.050 (1,27)
0.640 (16,26)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
12
13
30° TYP
1.115 (28,32)
0.840 (21,34)
4040180-5/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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