SN74AS757N-10 [TI]
AS SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDIP20;
| 型号： | SN74AS757N-10 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AS SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDIP20 驱动 输入元件 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总17页 (文件大小：1006K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SDAS040B − DECEMBER 1983 − REVISED JANUARY 1995
SN54AS756 . . . J PACKAGE
SN74AS756, SN74AS757 . . . DW OR N PACKAGE
(TOP VIEW)
• Open-Collector Outputs Drive Bus Lines or
Buffer Memory Address Registers
• Eliminate the Need for 3-State Overlap
Protection
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
2OE/2OE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
†
• pnp Inputs Reduce dc Loading
1Y1
2A4
1Y2
2A3
• Open-Collector Versions of ′AS240A and
′AS241
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
1Y3
13 2A2
12 1Y4
11
2A1
description
These octal buffers and line drivers are designed
specifically to improve the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters by eliminating the need for 3-state
overlap protection. The designer has a choice of
selected combinations of inverting and
noninverting outputs, symmetrical active-low
output-enable (OE) inputs, and complementary
OE and OE inputs. These devices feature high
fan-out and improved fan-in.
SN54AS756 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
1Y1
2A4
1Y2
2A3
1Y3
1A2
2Y3
1A3
2Y2
1A4
4
5
6
7
8
17
16
15
14
9 10 11 12 13
The SN54AS756 is characterized for operation
over the full military temperature range of −55°C
to 125°C. The SN74AS756 and SN74AS757 are
characterized for operation from 0°C to 70°C.
†
2OE for ′AS756 or 2OE for SN74AS757
‡
logic symbols
′AS756
SN74AS757
EN
1
1
EN
1OE
1OE
2
4
6
8
18
16
14
12
2
4
6
8
18
16
14
12
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
19
19
EN
2OE
EN
2OE
11
13
15
17
9
7
5
3
11
13
15
17
9
7
5
3
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
‡
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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Copyright 1995, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SDAS040B − DECEMBER 1983 − REVISED JANUARY 1995
logic diagrams (positive logic)
′AS756
SN74AS757
1
1
1OE
1OE
18
16
18
16
2
4
2
4
1Y1
1Y2
1Y3
1Y4
1Y1
1Y2
1Y3
1Y4
1A1
1A2
1A1
1A2
14
12
14
12
6
8
6
8
1A3
1A4
1A3
1A4
19
19
2OE
2OE
9
7
9
7
11
13
11
13
2Y1
2Y2
2Y1
2Y2
2A1
2A2
2A3
2A4
2A1
2A2
2A3
2A4
5
3
5
3
15
17
15
17
2Y3
2Y4
2Y3
2Y4
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range, T : SN54AS756 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
A
SN74AS756, SN74AS757 . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢉ ꢊꢋꢄꢌꢈꢍ ꢎꢏ ꢏꢐ ꢑꢀꢈꢄꢁꢒ ꢈꢌ ꢓꢁꢐꢈ ꢒ ꢑꢓ ꢔ ꢐꢑ
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SDAS040B − DECEMBER 1983 − REVISED JANUARY 1995
recommended operating conditions
SN74AS756
SN54AS756
SN74AS757
UNIT
MIN NOM
4.5
MAX
MIN NOM
MAX
V
V
V
V
Supply voltage
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output current
Operating free-air temperature
2
IH
0.7
5.5
48
0.8
5.5
64
V
IL
V
OH
I
mA
°C
OL
T
A
−55
125
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74AS756
SN54AS756
SN74AS757
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
−1.2
0.1
MIN TYP
MAX
−1.2
0.1
V
V
V
= 4.5 V,
= 4.5 V,
I = −18 mA
V
IK
CC
I
I
V
OH
= 5.5 V
mA
OH
CC
I
I
= 48 mA
= 64 mA
0.55
OL
V
V
= 4.5 V
V
OL
CC
0.55
0.1
20
OL
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 7 V
0.1
20
mA
I
CC
I
V = 2.7 V
µA
IH
CC
I
A inputs of
SN74AS757 only
−1
−1
I
V
CC
= 5.5 V,
V = 0.4 V
I
mA
mA
IL
All other inputs
−0.5
15
−0.5
15
Outputs high
Outputs low
Outputs high
Outputs low
9
9
′AS756
V
V
= 5.5 V
= 5.5 V
CC
51
21
61
80
51
21
61
80
I
CC
33
33
SN74AS757
CC
95
95
†
All typical values are at V
CC
= 5 V, T = 25°C.
A
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SDAS040B − DECEMBER 1983 − REVISED JANUARY 1995
switching characteristics (see Figure 1)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
FROM
TO
(OUTPUT)
†
PARAMETER
(INPUT)
UNIT
T
A
= MIN to MAX
SN54AS756
SN74AS756
MIN
3
MAX
20
MIN
3
MAX
19
t
t
t
t
PLH
PHL
PLH
PHL
A
ns
ns
Y
Y
1
7
1
6
3
22
3
19.5
7.5
OE
1
8.5
1
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
switching characteristics (see Figure 1)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
FROM
TO
(OUTPUT)
†
PARAMETER
(INPUT)
UNIT
T
A
= MIN to MAX
SN74AS757
MIN
3
MAX
18.5
6
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PLH
PHL
A
ns
ns
ns
Y
1
3
20
1OE
2OE
1Y
2Y
1
7
3
21
1
7.5
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SDAS040B − DECEMBER 1983 − REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
t
w
h
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
[3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
V
OL
0.3 V
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
[0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-90563012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
90563012A
SNJ54AS
756FK
5962-9056301RA
5962-9056301SA
ACTIVE
ACTIVE
CDIP
CFP
J
20
20
1
1
TBD
TBD
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-9056301RA
SNJ54AS756J
W
Call TI
5962-9056301SA
SNJ54AS756W
SN54AS756J
ACTIVE
ACTIVE
CDIP
SOIC
J
20
20
1
A42
N / A for Pkg Type
-55 to 125
0 to 70
SN54AS756J
SN74AS756DW
DW
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AS756
SN74AS756DWE4
SN74AS756DWG4
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
20
20
25
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
AS756
AS756
AS756
Green (RoHS
& no Sb/Br)
SN74AS756DWR
SN74AS756DWRE4
SN74AS756DWRG4
SN74AS756N
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
SOIC
SOIC
SOIC
PDIP
DW
DW
DW
N
20
20
20
20
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
0 to 70
0 to 70
0 to 70
0 to 70
Call TI
Call TI
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74AS756N
SN74AS756N
AS757
SN74AS756NE4
SN74AS757DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
N
20
20
20
20
20
20
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
DW
DW
DW
DW
DW
25
Green (RoHS
& no Sb/Br)
SN74AS757DWE4
SN74AS757DWG4
SN74AS757DWR
SN74AS757DWRE4
25
Green (RoHS
& no Sb/Br)
AS757
25
Green (RoHS
& no Sb/Br)
AS757
2000
2000
Green (RoHS
& no Sb/Br)
AS757
Green (RoHS
& no Sb/Br)
AS757
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SN74AS757DWRG4
SN74AS757N
ACTIVE
SOIC
PDIP
PDIP
LCCC
DW
20
20
20
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
POST-PLATE
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
AS757
ACTIVE
ACTIVE
ACTIVE
N
N
20
20
1
Pb-Free
(RoHS)
0 to 70
SN74AS757N
SN74AS757N
SN74AS757NE4
SNJ54AS756FK
Pb-Free
(RoHS)
0 to 70
FK
TBD
-55 to 125
5962-
90563012A
SNJ54AS
756FK
SNJ54AS756J
SNJ54AS756W
ACTIVE
ACTIVE
CDIP
CFP
J
20
20
1
1
TBD
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-9056301RA
SNJ54AS756J
W
Call TI
5962-9056301SA
SNJ54AS756W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54AS756, SN74AS756 :
Catalog: SN74AS756
•
Military: SN54AS756
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AS757DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
SN74AS757DWR
2000
Pack Materials-Page 2
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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