SN74AS822 [TI]
10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS; 10位总线接口触发器具有三态输出
| 型号： | SN74AS822 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS |
| 文件： | 总6页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54AS821, SN54AS822, SN74AS821, SN74AS822
10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230 – D2825, DECEMBER 1983 – REVISED JANUARY 1986
SN54AS821 . . . JT PACKAGE
SN74AS821 . . . DW OR NT PACKAGE
(TOP VIEW)
• Functionally Equivalent to AMD’s AM29821
and AM29822
•
•
Provides Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
OC
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
1
24
23
22
21
20
19
18
17
16
15
14
13
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
2
Outputs Have Undershoot Protection
Circuitry
3
4
5
•
•
Powerup High-impedance State
6
Package Options Include Plastic Small
Outline Packages, Both Plastic and
Ceramic Chip Carriers, and Standard
Plastic and Ceramic 300-mil DIPs
7
8
9
9D
10D
GND
10
11
12
•
•
Buffered Control Inputs to Reduce DC
Loading Effects
V
CC
Dependable Texas Instruments Quality and
Reliability
description
These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly-capacitive or relatively
low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports,
bidirectional bus drivers with parity, and working registers.
The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock the Q outputs on
the ’AS821 will be true, and on the ’AS822 will be complementary to the data input.
A buffered output-control input can be used to place the ten outputs in either a normal logic state (high or low
levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive the bus lines in a
bus-organized system without need for interface or pullup components. The output control (OC) does not affect
the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs
are in the high-impedance state.
The SN54AS’ family is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AS’ family is characterized for operation from 0°C to 70°C.
SN54AS821 . . . FK PACKAGE
SN74AS821 . . . FN PACKAGE
SN54AS822 . . . JT PACKAGE
SN74AS822 . . . DW OR NT PACKAGE
SN54AS822 . . . FK PACKAGE
SN74AS822 . . . FN PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
OC
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
1
24
23
22
21
20
19
18
17
16
15
14
13
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
10Q
CLK
2
3
4
4
3
2
1
28 27 26
3 2 1 28 27 26
5
5
25 3Q
25 3Q
3D
4D
5D
NC
6D
7D
8D
3D
4D
5D
NC
6D
7D
8D
4
6
4Q
5Q
NC
6Q
7Q
8Q
6
4Q
5Q
NC
6Q
7Q
8Q
24
23
22
21
20
19
24
23
22
21
20
19
5
7
7
6
8
8
7
9
9
8
10
10
9
11
11
9D
10D
GND
10
11
12
12 13 14 15 16 17 18
12 13 14 15 16 17 18
NC–No internal connection
Copyright 1986, Texas Instruments Incorporated
5BASIC
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS821, SN74AS821
10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230 – D2825, DECEMBER 1983 – REVISED JANUARY 1986
’AS821 FUNCTION TABLE
’AS821 logic diagram (positive logic)
(each flip-flop)
INPUTS OUTPUT
OC
L
CLK
D
H
L
1
Q
H
L
OC
↑
↑
L
13
2
CLK
1D
L
L
X
X
X
Q
0
Z
C1
1D
23
H
1Q
C1
1D
†
22
21
’AS821 logic symbol
2Q
3Q
3
2D
1
OC
EN
C1
13
CLK
C1
1D
4
5
2
23
3D
4D
1D
1D
1Q
3
4
22
21
2D
3D
2Q
3Q
C1
1D
5
6
20
19
20
19
4D
5D
4Q
5Q
4Q
5Q
7
18
17
16
15
14
6D
7D
6Q
7Q
8Q
9Q
8
C1
1D
9
8D
10
11
6
9D
5D
10D
10Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
C1
1D
18
17
16
6Q
7Q
8Q
7
8
6D
7D
C1
1D
C1
1D
9
8D
9D
C1
1D
15
14
9Q
10
C1
1D
10Q
11
10D
Pin numbers shown are for DW, JT, and NT packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS822, SN74AS822
10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230 – D2825, DECEMBER 1983 – REVISED JANUARY 1986
’AS822 FUNCTION TABLE
(each flip-flop)
INPUTS OUTPUT
’AS822 logic diagram positive logic
OC
L
CLK
D
H
L
Q
H
L
1
OC
↑
↑
L
13
CLK
L
L
X
X
X
Q
0
Z
C1
1D
23
H
1Q
2
1D
C1
1D
†
’AS822 logic symbol
22
21
2Q
3Q
3
2D
1
OC
EN
C1
13
CLK
C1
1D
2
23
4
5
1D
1D
1Q
3D
4D
3
4
22
21
2D
3D
2Q
3Q
C1
1D
5
6
20
19
20
19
4D
5D
4Q
5Q
4Q
5Q
7
18
17
16
15
14
6D
7D
6Q
7Q
8Q
9Q
8
9
C1
1D
8D
10
11
6
9D
5D
10D
10Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
C1
1D
18
17
16
6Q
7Q
8Q
7
8
6D
7D
C1
1D
C1
1D
9
8D
9D
C1
1D
15
14
9Q
10
C1
1D
10Q
11
10D
Pin numbers shown are for DW, JT, and NT packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS821, SN54AS822, SN74AS821, SN74AS822
10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230 – D2825, DECEMBER 1983 – REVISED JANUARY 1986
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54AS821, SN54AS822 . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
SN74AS821, SN74AS822 . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
recommended operating conditions
SN54AS821
SN54AS822
MIN NOM
SN74AS821
SN74AS822
UNIT
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
High-level input voltage
Low-level input voltage
0.8
–24
32
0.8
–24
48
V
IL
I
I
t
t
t
High-level output current
Low-level output current
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
Operating free-air temperature
mA
mA
ns
ns
ns
°C
OH
OL
w
9
7
8
6
0
0
su
h
0
T
A
–55
125
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS821
SN74AS821
PARAMETER
TEST CONDITIONS
SN54AS822
SN74AS822
UNIT
V
‡
TYP
‡
TYP
MIN
MAX
MIN
MAX
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V to 5.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
I = –18 mA
–1.2
–1.2
IK
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
I
I
I
I
I
I
= –2 mA
= –15 mA
= –24 mA
= 32 mA
= 48 mA
= 2. 7 V
V
–2
V
–2
OH
OH
OH
OL
OL
CC
2.4
CC
2.4
3.2
3.2
V
OH
2
2
0.25
0.5
V
V
OL
0.35
0.5
50
I
I
I
I
I
I
V
V
50
–50
0.1
µA
µA
OZH
OZL
I
O
O
= 0.4 V
–50
0.1
V = 7 V
I
V = 2.7 V
I
V = 0 .4 V
I
mA
µA
20
20
IH
–0.5
–112
88
–0.5
–112
88
mA
mA
IL
‡
V
O
= 2.25 V
–30
–30
O
Outputs high
Outputs low
55
68
70
55
68
70
55
68
70
55
68
70
’AS821
’AS822
109
113
88
109
113
88
Outputs disabled
Outputs high
Outputs low
I
V
CC
= 5.5 V
mA
CC
109
113
109
113
Outputs disabled
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS821, SN54AS822, SN74AS821, SN74AS822
10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230 – D2825, DECEMBER 1983 – REVISED JANUARY 1986
switching characteristics (see Note 1)
V
= 4.5 V to 5.5 V,
= 50 pF,
CC
C
L
R1 = 500 Ω,
FROM
PARAMETER
TO
R2 = 500 Ω,
†
T = MIN to MAX
A
UNIT
(INPUT)
(OUTPUT)
SN54AS821
SN54AS822
SN74AS821
SN74AS822
MIN
3.5
3.5
4
MAX
9
MIN
3.5
3.5
4
MAX
7.5
10.5
11
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PZL
CLK
OC
OC
Any Q
Any Q
Any Q
ns
ns
ns
11.5
12
4
13
4
12
2
10
2
8
2
10
2
8
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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