SN74AS825NT [TI]
AS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP24;
| 型号： | SN74AS825NT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP24 触发器 输出元件 |
| 文件： | 总7页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54AS825A, SN74AS825A
8-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS020B – JUNE 1984 – REVISED AUGUST 1995
SN54AS825A . . . JT PACKAGE
SN74AS825A . . . DW OR NT PACKAGE
(TOP VIEW)
• Functionally Equivalent to AMD’s AM29825
• Improved I Specifications
OH
• Multiple Output Enables Allow Multiuser
Control of the Interface
OE1
OE2
1D
2D
3D
4D
5D
6D
7D
V
CC
1
2
3
4
5
6
7
8
9
24
23 OE3
22 1Q
21 2Q
20 3Q
19 4Q
18 5Q
17 6Q
16 7Q
15 8Q
14 CLKEN
13 CLK
• Outputs Have Undershoot-Protection
Circuitry
• Power-Up High-Impedance State
• Buffered Control Inputs Reduce dc
Loading Effects
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
8D 10
CLR 11
GND 12
description
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. These devices
are particularly suitable for implementing
multiuser registers, I/O ports, bidirectional bus
drivers, and working registers.
SN54AS825A . . . FK PACKAGE
(TOP VIEW)
4
3
2
1
28 27 26
25
2D
3D
4D
NC
5D
6D
7D
2Q
3Q
4Q
NC
5Q
6Q
7Q
5
With the clock-enable (CLKEN) input low, the
eight D-type edge-triggered flip-flops enter data
on the low-to-high transitions of the clock (CLK)
input. Taking CLKEN high disables the clock
buffer, latching the outputs. These devices have
noninverting data (D) inputs. Taking the clear
(CLR) input low causes the eight Q outputs to go
low independently of the clock.
24
23
22
21
20
19
6
7
8
9
10
11
12 13 14 15 16 17 18
Multiuser buffered output-enable (OE1, OE2, and
OE3) inputs can be used to place the eight outputs
in either a normal logic state (high or low logic
NC – No internal connection
level) or
a high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The high-
impedance state and increased drive provide the
capability to drive bus lines without interface or
pullup components.
The output enables do not affect the internal operation of the flip-flops. Old data can be retained or new data
can be entered while the outputs are in the high-impedance state.
The SN54AS825A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AS825A is characterized for operation from 0°C to 70°C.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS825A, SN74AS825A
8-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS020B – JUNE 1984 – REVISED AUGUST 1995
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
†
OE
L
CLR CLKEN CLK
D
X
H
L
L
H
H
H
X
X
L
X
↑
L
H
L
L
L
L
↑
L
H
X
X
X
X
X
Q
0
H
Z
†
OE = H if any of OE1, OE2, or OE3 are high.
OE = L if all of OE1, OE2, or OE3 are low.
‡
logic symbol
1
&
OE1
OE2
OE3
CLR
2
EN
23
11
R
14
13
G1
CLKEN
CLK
1C2
3
22
1D
2D
1Q
4
21
20
19
18
17
16
15
2D
3D
4D
5D
6D
7D
8D
2Q
3Q
4Q
5Q
6Q
7Q
8Q
5
6
7
8
9
10
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS825A, SN74AS825A
8-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS020B – JUNE 1984 – REVISED AUGUST 1995
logic diagram (positive logic)
1
OE1
2
OE2
23
OE3
11
CLR
14
CLKEN
R
13
CLK
22
C1
1D
1Q
3
1D
To Seven Other Channels
Pin numbers shown are for the DW, JT, and NT packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, T : SN54AS825A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74AS825A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS825A, SN74AS825A
8-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS020B – JUNE 1984 – REVISED AUGUST 1995
recommended operating conditions
SN54AS825A
MIN NOM MAX
SN74AS825A
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
IH
0.7
–24
32
0.8
–24
48
V
IL
I
mA
mA
OH
OL
I
CLR low
7
9.5
8
4
8
8
6
6
0
0
t *
Pulse duration
ns
w
CLK high or low
CLR inactive
Data
t *
su
7
ns
Setup time before CLK↑
CLKEN high or low
CLKEN low or data
10
0
t *
h
Hold time after CLK↑
ns
T
A
Operating free-air temperature
–55
125
70
°C
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS825A
SN74AS825A
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
I
I
= –2 mA
= –15 mA
= –24 mA
= 32 mA
= 48 mA
= 2.7 V
V
–2
V
–2
CC
OH
OH
OH
OL
OL
CC
2.4
CC
2.4
V
OH
3.2
0.3
3.2
V
V
= 4.5 V
= 4.5 V
CC
CC
2
2
0.5
V
OL
V
V
0.35
0.5
50
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
O
50
–50
0.1
µA
µA
OZH
OZL
I
V = 0.4 V
I
–50
0.1
V = 7 V
I
mA
µA
V = 2.7 V
I
20
20
IH
V = 0.4 V
I
–0.5
–112
73
–0.5
–112
73
mA
mA
IL
‡
V
O
= 2.25 V
–30
–30
O
Outputs high
Outputs low
45
56
59
45
56
59
I
V
CC
= 5.5 V
90
90
mA
CC
Outputs disabled
95
95
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS825A, SN74AS825A
8-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS020B – JUNE 1984 – REVISED AUGUST 1995
switching characteristics (see Figure 1)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
R1 = 500 Ω,
R2 = 500 Ω,
T
A
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
UNIT
†
= MIN to MAX
SN54AS825A SN74AS825A
MIN
3.5
3.5
3.5
4
MAX
9
MIN
3.5
3.5
3.5
4
MAX
7.5
13
t
t
t
t
t
t
t
PLH
PHL
PHL
PZH
PZL
PHZ
PLZ
CLK
CLR
OE
ns
ns
ns
Any Q
Any Q
Any Q
13.5
16.5
12
15.5
11
4
13
4
12
1
10
1.5
1.5
8
ns
OE
Any Q
1
10
8
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS825A, SN74AS825A
8-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS020B – JUNE 1984 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
h
t
w
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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