SN74AUC1G125YEPR [TI]
SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT; 具有三态输出单总线缓冲器门型号: | SN74AUC1G125YEPR |
厂家: | TEXAS INSTRUMENTS |
描述: | SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT |
文件: | 总13页 (文件大小:317K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN74AUC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES382G – MARCH 2002 – REVISED JUNE 2003
DBV OR DCK PACKAGE
(TOP VIEW)
Available in the Texas Instruments
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
1
2
3
5
4
OE
A
GND
V
Y
CC
I
Supports Partial-Power-Down Mode
off
Operation
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
Sub 1-V Operable
Max t of 2.5 ns at 1.8 V
pd
Low Power Consumption, 10-µA Max I
3 4
2
GND
A
OE
Y
V
CC
8-mA Output Drive at 1.8 V
1 5
CC
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This bus buffer gate is operational at 0.8-V to 2.7-V V , but is designed specifically for 1.65-V to 1.95-V V
CC
operation.
CC
The SN74AUC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable
(OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
‡
NanoStar
SN74AUC1G125YEAR
SN74AUC1G125YZAR
SN74AUC1G125YEPR
SN74AUC1G125YZPR
WCSP (DSBGA) – YEA
NanoFree
WCSP (DSBGA) – YZA (Pb-free)
Tape and reel
_ _ _UM_
NanoStar – WCSP (DSBGA)
0.23-mm Large Bump – YEP
–40°C to 85°C
NanoFree – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SOT (SOT-23) – DBV
Tape and reel SN74AUC1G125DBVR
Tape and reel SN74AUC1G125DCKR
U25_
UM_
SOT (SC-70) – DCK
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES382G – MARCH 2002 – REVISED JUNE 2003
description/ordering information (continued)
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
H
L
H
X
Z
logic diagram (positive logic)
1
2
OE
A
4
Y
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous current through V
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
JA
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 132°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder“recommendedoperatingconditions”isnotimplied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES382G – MARCH 2002 – REVISED JUNE 2003
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
V
Supply voltage
0.8
2.7
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
V
CC
V
High-level input voltage
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
= 0.8 V
0.65 × V
V
V
CC
1.7
0
0.35 × V
0.7
V
IL
Low-level input voltage
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
CC
V
V
Input voltage
0
0
3.6
V
V
I
Output voltage
V
CC
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
–0.7
–3
–5
–8
–9
0.7
3
= 1.1 V
I
High-level output current
Low-level output current
= 1.4 V
mA
mA
OH
OL
= 1.65 V
= 2.3 V
= 0.8 V
= 1.1 V
I
= 1.4 V
5
= 1.65 V
8
= 2.3 V
9
= 0.8 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
20
10
3
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
–40
85
°C
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES382G – MARCH 2002 – REVISED JUNE 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
V –0.1
CC
TYP
MAX
UNIT
V
CC
I
I
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –0.7 mA
= –3 mA
= –5 mA
= –8 mA
= –9 mA
= 100 µA
= 0.7 mA
= 3 mA
0.8 V to 2.7 V
0.8 V
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
0.55
1.1 V
0.8
1
V
OH
V
1.4 V
1.65 V
2.3 V
1.2
1.8
0.8 V to 2.7 V
0.8 V
0.2
0.25
1.1 V
0.3
0.4
0.45
0.6
5
V
OL
V
= 5 mA
1.4 V
= 8 mA
1.65 V
2.3 V
= 9 mA
I
I
I
I
A or OE input V = V or GND
CC
0 to 2.7 V
0
µA
µA
µA
µA
pF
I
I
V or V = 2.7 V
10
off
I
O
V
= V or GND
CC
2.7 V
10
OZ
CC
O
V = V
or GND,
or GND
I = 0
O
0.8 V to 2.7 V
2.5 V
10
I
CC
CC
C
C
V = V
2.5
5.5
i
I
V
= V or GND
CC
2.5 V
pF
o
O
†
All typical values are at T = 25°C.
A
switching characteristics over recommended operating free-air temperature range, C = 15 pF
L
(unless otherwise noted) (see Figure 1)
V
= 1.2 V
V
= 1.5 V
V
= 1.8 V
V
= 2.5 V
CC
0.1 V
CC
0.1 V
CC
0.15 V
CC
0.2 V
V
CC
= 0.8 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
MIN MAX
MIN MAX
MIN TYP MAX
MIN MAX
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
t
A
4.7
5.4
4.8
0.8
0.7
1.4
3.6
4.1
4.3
0.4
0.5
1.4
2.3
2.6
4
ns
ns
ns
Y
Y
Y
pd
t
en
OE
OE
t
dis
‡
This information was not available at the time of publication.
switching characteristics over recommended operating free-air temperature range, C = 30 pF
L
(unless otherwise noted) (see Figure 1)
V
= 1.8 V
V
= 2.5 V
CC
0.15 V
CC
0.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN TYP MAX
MIN MAX
t
A
0.7
1
1.5
1.6
2.2
2.5
2.6
3.1
0.9
1.1
0.8
1.7
1.9
1.7
ns
ns
ns
Y
Y
Y
pd
t
en
OE
OE
t
1.8
dis
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES382G – MARCH 2002 – REVISED JUNE 2003
operating characteristics, T = 25°C
A
V
= 0.8 V
CC
TYP
V
= 1.2 V
CC
TYP
V
= 1.5 V
CC
TYP
V
= 1.8 V
CC
TYP
V
= 2.5 V
CC
TYP
TEST
PARAMETER
UNIT
CONDITIONS
Outputs
enabled
14
14
14
15
2
16
Power
dissipation
capacitance
C
f = 10 MHz
pF
pd
Outputs
disabled
1.5
1.5
1.5
2.5
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AUC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES382G – MARCH 2002 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
S1
R
L
t
t
/t
Open
From Output
Under Test
PLH PHL
t
/t
2 × V
CC
GND
PLZ PZL
/t
PHZ PZH
C
L
R
L
(see Note A)
V
∆
C
L
R
V
CC
L
0.8 V
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
0.1 V
0.1 V
15 pF
1.2 V 0.1 V
1.5 V 0.1 V
1.8 V 0.15 V
2.5 V 0.2 V
1.8 V 0.15 V
2.5 V 0.2 V
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
LOAD CIRCUIT
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
V
CC
Timing Input
V
CC
/2
0 V
t
w
t
t
h
su
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
V
CC
/2
V
CC
/2
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
Input
0 V
0 V
t
t
t
t
t
PHL
/2
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
V
V
V
OH
CC
V
/2
/2
V
V
/2
/2
V
CC
Output
CC
CC
S1 at 2 × V
(see Note B)
V
V
CC
OL
∆
OL
OL
t
t
t
PLH
/2
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– V
OH
∆
V
CC
V
CC
CC
Output
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, slew rate ≥ 1 V/ns.
O
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
PHL
.
en
.
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002
DCK (R-PDSO-G5)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,10
0,65
5
4
0,13 NOM
1,40 2,40
1,10 1,80
1
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
0,10
1,10
0,80
0,10
0,00
4093553-2/D 01/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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