SN74AUC1G86DCKR [TI]
SINGLE 2-INPUT EXCLUSIVE OR GATE; 单路2输入异或门
| 型号： | SN74AUC1G86DCKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SINGLE 2-INPUT EXCLUSIVE OR GATE |
| 文件： | 总13页 (文件大小：357K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊ
ꢀꢋ ꢁꢈ ꢌ ꢍ ꢎ ꢏꢋꢁ ꢐꢅꢑ ꢍꢒ ꢆꢌ ꢅꢀꢋ ꢓꢍ ꢏꢔ ꢕ ꢈ ꢄꢑꢍ
SCES389G − MARCH 2002 − REVISED FEBRUARY 2004
DBV OR DCK PACKAGE
(TOP VIEW)
D
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
1
2
3
5
4
A
B
GND
V
Y
CC
D
I
Supports Partial-Power-Down Mode
off
Operation
YEA OR YZA PACKAGE
(BOTTOM VIEW)
D
D
D
D
D
Sub 1-V Operable
Max t of 2.5 ns at 1.8 V
pd
Low Power Consumption, 10-µA Max I
3 4
2
GND
B
Y
V
CC
8-mA Output Drive at 1.8 V
1 5
A
CC
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This single 2-input exclusive-OR gate is operational at 0.8-V to 2.7-V V , but is designed specifically for 1.65-V
CC
to 1.95-V V
operation.
CC
The SN74AUC1G86 performs the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.
A common application is as a true/complement element. If the input is low, the other input is reproduced in true
form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
‡
NanoStar
WCSP (DSBGA) − YEA
Tape and reel SN74AUC1G86YEAR
_ _ _UH_
NanoFree
WCSP (DSBGA) − YZA (Pb-free)
Tape and reel SN74AUC1G86YZAR
−40°C to 85°C
SOT (SOT-23) − DBV
Tape and reel SN74AUC1G86DBVR
Tape and reel SN74AUC1G86DCKR
U86_
UH_
SOT (SC-70) − DCK
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCES389G − MARCH 2002 − REVISED FEBRUARY 2004
FUNCTION TABLE
INPUTS
OUTPUT
Y
A
B
L
L
L
L
H
H
L
H
L
H
H
H
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative
logic symbols.
EXCLUSIVE OR
=1
These are five equivalent exclusive-OR symbols valid for an SN74AUC1G86 gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT
=
EVEN-PARITY ELEMENT
2k
ODD-PARITY ELEMENT
2k + 1
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous current through V
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
JA
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCES389G − MARCH 2002 − REVISED FEBRUARY 2004
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
V
Supply voltage
0.8
2.7
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
V
CC
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
= 0.8 V
0.65×V
V
High-level input voltage
V
V
CC
1.7
0
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
0.35×V
V
Low-level input voltage
CC
IL
0.7
3.6
V
V
Input voltage
0
0
V
V
I
Output voltage
V
CC
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
= 1.1 V
= 1.4 V
= 1.65 V
= 2.3 V
= 0.8 V
= 1.1 V
= 1.4 V
= 1.65 V
= 2.3 V
−0.7
−3
−5
−8
−9
0.7
3
I
High-level output current
Low-level output current
mA
mA
OH
5
I
OL
8
9
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
20
85
ns/V
T
A
−40
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
V −0.1
CC
TYP
MAX
UNIT
V
CC
I
I
I
I
I
I
I
I
I
I
I
I
= −100 µA
= −0.7 mA
= −3 mA
= −5 mA
= −8 mA
= −9 mA
= 100 µA
= 0.7 mA
= 3 mA
0.8 V to 2.7 V
0.8 V
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
0.55
1.1 V
0.8
V
OH
V
1.4 V
1
1.2
1.8
1.65 V
2.3 V
0.8 V to 2.7 V
0.8 V
0.2
0.25
1.1 V
0.3
0.4
0.45
0.6
5
V
OL
V
= 5 mA
1.4 V
= 8 mA
1.65 V
2.3 V
= 9 mA
I
I
I
A or B input
V = V
CC
or GND
0 to 2.7 V
0
µA
µA
µA
pF
I
I
V or V = 2.7 V
10
off
I
O
V = V
or GND,
or GND
I = 0
O
0.8 V to 2.7 V
2.5 V
10
CC
I
CC
C
V = V
2.5
i
I
CC
†
All typical values are at T = 25°C.
A
3
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SCES389G − MARCH 2002 − REVISED FEBRUARY 2004
switching characteristics over recommended operating free-air temperature range, C = 15 pF
L
(unless otherwise noted) (see Figure 1)
V
= 1.2 V
0.1 V
V
= 1.5 V
0.1 V
V
= 1.8 V
V
= 2.5 V
0.2 V
CC
CC
CC
0.15 V
CC
V
CC
= 0.8 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
MIN MAX
MIN MAX
MIN TYP MAX
MIN MAX
A
B
5.5
5
0.8
0.8
3.8
3.8
0.5
0.5
2.6
2.6
0.4
0.4
1
1
1.7
1.7
0.3
0.3
1.3
1.2
t
pd
ns
Y
switching characteristics over recommended operating free-air temperature range, C = 30 pF
L
(unless otherwise noted) (see Figure 1)
V
= 1.8 V
V
= 2.5 V
CC
CC
0.2 V
FROM
(INPUT)
TO
(OUTPUT)
0.15 V
TYP
1.5
PARAMETER
UNIT
MIN
MAX
MIN
MAX
A
B
0.8
0.8
2.6
0.7
0.7
2
t
pd
ns
Y
1.5
2.6
2
operating characteristics, T = 25°C
A
V
= 0.8 V
CC
TYP
V
= 1.2 V
CC
TYP
V
CC
= 1.5 V
V
CC
= 1.8 V
V = 2.5 V
CC
TEST
PARAMETER
UNIT
CONDITIONS
TYP
TYP
TYP
Power dissipation
capacitance
C
f = 10 MHz
16
16
16.5
17
18.5
pF
pd
4
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SCES389G − MARCH 2002 − REVISED FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
S1
S1
Open
R
L
t
t
/t
Open
From Output
Under Test
PLH PHL
GND
t
/t
2 × V
CC
GND
PLZ PZL
/t
PHZ PZH
C
L
R
L
(see Note A)
V
∆
C
L
R
V
CC
L
0.8 V
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
0.1 V
0.1 V
15 pF
1.2 V 0.1 V
1.5 V 0.1 V
1.8 V 0.15 V
2.5 V 0.2 V
1.8 V 0.15 V
2.5 V 0.2 V
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
LOAD CIRCUIT
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
V
CC
Timing Input
V
CC
/2
0 V
t
w
t
t
h
su
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
V
CC
/2
V
CC
/2
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
Input
0 V
0 V
t
t
t
t
t
PHL
/2
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
V
V
V
OH
CC
V
/2
/2
V
V
/2
/2
V
CC
Output
CC
CC
S1 at 2 × V
(see Note B)
V
V
CC
OL
∆
OL
OL
t
t
t
PLH
/2
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
− V
OH
∆
V
CC
V
CC
CC
Output
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, slew rate ≥ 1 V/ns.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
are the same as t
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Apr-2005
PACKAGING INFORMATION
Orderable Device
SN74AUC1G86DBVR
SN74AUC1G86DCKR
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
DCK
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AUC1G86YEAR
SN74AUC1G86YEPR
SN74AUC1G86YZAR
ACTIVE
ACTIVE
ACTIVE
WCSP
WCSP
WCSP
YEA
YEP
YZA
5
5
5
3000
3000
3000
TBD
TBD
SNPB
SNPB
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Pb-Free
(RoHS)
SNAGCU
SN74AUC1G86YZPR
ACTIVE
WCSP
YZP
5
3000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002
DCK (R-PDSO-G5)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,10
0,65
5
4
0,13 NOM
1,40 2,40
1,10 1,80
1
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
0,10
1,10
0,80
0,10
0,00
4093553-2/D 01/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
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