SN74AUC2G32 [TI]
DUAL 2 INPUT POSITIVE OR GATE; 双2输入正或门
| 型号： | SN74AUC2G32 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL 2 INPUT POSITIVE OR GATE |
| 文件： | 总10页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢇ
ꢊꢅꢄ ꢋ ꢇ ꢌꢍꢁ ꢎꢅꢏ ꢎꢐ ꢀꢍ ꢏ ꢍꢑꢒꢌ ꢐ ꢓ ꢈ ꢄꢏꢒ
SCES478A − AUGUST 2003 − REVISED NOVEMBER 2003
DCT OR DCU PACKAGE
(TOP VIEW)
D
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
1A
1B
V
CC
1
2
3
4
8
7
6
5
1Y
2B
2A
2Y
D
I
Supports Partial-Power-Down Mode
off
GND
Operation
D
D
D
D
D
Sub 1-V Operable
YEP OR YZP PACKAGE
(BOTTOM VIEW)
Max t of 1.5 ns at 1.8 V
pd
Low Power Consumption, 10 µA at 1.8 V
4 5
3 6
2 7
1 8
GND
2Y
1B
2A
2B
1Y
8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
1A
V
CC
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This dual 2-input positive-OR gate is operational at 0.8-V to 2.7-V V , but is designed specifically for 1.65-V
CC
to 1.95-V V
operation.
CC
The SN74AUC2G32 performs the Boolean function Y + A ) B or Y + A • B in positive logic.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
For more information about AUC Little Logic devices, please refer to the TI application report, Applications of
Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
SN74AUC2G32YEPR
SN74AUC2G32YZPR
Tape and reel
_ _ _UG_
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
−40°C to 85°C
SSOP − DCT
Tape and reel
Tape and reel
SN74AUC2G32DCTR
SN74AUC2G32DCUR
U32_ _ _
U32_
VSSOP − DCU
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and
one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
ꢎ
ꢎ
ꢓ
ꢐ
ꢣ
ꢊ
ꢞ
ꢅ
ꢆ
ꢜ
ꢏ
ꢝ
ꢍ
ꢗ
ꢐ
ꢕ
ꢁ
ꢖ
ꢊ
ꢄ
ꢏ
ꢄ
ꢔ
ꢕ
ꢟ
ꢖ
ꢗ
ꢝ
ꢘ
ꢙ
ꢚ
ꢚ
ꢛ
ꢛ
ꢔ
ꢔ
ꢗ
ꢗ
ꢕ
ꢕ
ꢔ
ꢜ
ꢜ
ꢠ
ꢝ
ꢞ
ꢘ
ꢘ
ꢟ
ꢟ
ꢕ
ꢛ
ꢚ
ꢙ
ꢜ
ꢜ
ꢗ
ꢖ
ꢠ
ꢏꢟ
ꢞ
ꢡ
ꢜ
ꢢ
ꢔ
ꢝ
ꢚ
ꢜ
ꢛ
ꢔ
ꢛ
ꢗ
ꢘ
ꢕ
ꢞ
ꢣ
ꢚ
ꢕ
ꢛ
ꢛ
ꢟ
ꢜ
ꢤ
Copyright 2003, Texas Instruments Incorporated
ꢘ
ꢗ
ꢝ
ꢛ
ꢗ
ꢘ
ꢙ
ꢛ
ꢗ
ꢜ
ꢠ
ꢔ
ꢖ
ꢔ
ꢝ
ꢟ
ꢘ
ꢛ
ꢥ
ꢛ
ꢟ
ꢘ
ꢗ
ꢖ
ꢦ
ꢚ
ꢍ
ꢕ
ꢙ
ꢟ
ꢜ
ꢛ
ꢚ
ꢕ
ꢣ
ꢚ
ꢘ
ꢣ
ꢧ
ꢚ
ꢛ ꢟ ꢜ ꢛꢔ ꢕꢩ ꢗꢖ ꢚ ꢢꢢ ꢠꢚ ꢘ ꢚ ꢙ ꢟ ꢛ ꢟ ꢘ ꢜ ꢤ
ꢘ
ꢘ
ꢚ
ꢕ
ꢛ
ꢨ
ꢤ
ꢎ
ꢘ
ꢗ
ꢣ
ꢞ
ꢝ
ꢛ
ꢔ
ꢗ
ꢕ
ꢠ
ꢘ
ꢗ
ꢝ
ꢟ
ꢜ
ꢜ
ꢔ
ꢕ
ꢩ
ꢣ
ꢗ
ꢟ
ꢜ
ꢕ
ꢗ
ꢛ
ꢕ
ꢟ
ꢝ
ꢟ
ꢜ
ꢜ
ꢚ
ꢘ
ꢔ
ꢢ
ꢨ
ꢔ
ꢕ
ꢝ
ꢢ
ꢞ
ꢣ
ꢟ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉ ꢇ
ꢊ ꢅꢄꢋ ꢇ ꢌꢍ ꢁꢎ ꢅꢏ ꢎ ꢐꢀ ꢍ ꢏꢍ ꢑ ꢒꢌ ꢐꢓ ꢈ ꢄꢏꢒ
SCES478A − AUGUST 2003 − REVISED NOVEMBER 2003
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
B
X
H
L
H
X
L
H
H
L
logic diagram (positive logic)
1
2
1A
1B
7
3
1Y
2Y
5
6
2A
2B
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous current through V
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 2): DCT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W
JA
DCU package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 102°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢇ
ꢊꢅꢄ ꢋ ꢇ ꢌꢍꢁ ꢎꢅꢏ ꢎꢐ ꢀꢍ ꢏ ꢍꢑꢒꢌ ꢐ ꢓ ꢈ ꢄꢏꢒ
SCES478A − AUGUST 2003 − REVISED NOVEMBER 2003
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
V
Supply voltage
0.8
2.7
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
V
CC
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
= 0.8 V
0.65 × V
V
High-level input voltage
V
V
CC
1.7
0
0.35 × V
0.7
= 1.1 V to 1.95 V
= 2.3 V to 2.7 V
V
Low-level input voltage
CC
IL
V
V
Input voltage
0
0
3.6
V
V
I
Output voltage
V
CC
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V
= 1.1 V
= 1.4 V
= 1.65 V
= 2.3 V
= 0.8 V
= 1.1 V
= 1.4 V
= 1.65 V
= 2.3 V
−0.7
−3
−5
−8
−9
0.7
3
I
High-level output current
Low-level output current
mA
mA
OH
5
I
OL
8
9
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
20
85
ns/V
T
A
−40
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
−0.1
TYP
MAX
UNIT
V
CC
I
I
I
I
I
I
I
I
I
I
I
I
= −100 µA
= −0.7 mA
= −3 mA
= −5 mA
= −8 mA
= −9 mA
= 100 µA
= 0.7 mA
= 3 mA
0.8 V to 2.7 V
0.8 V
V
CC
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
0.55
1.1 V
0.8
1
V
OH
V
1.4 V
1.65 V
2.3 V
1.2
1.8
0.8 V to 2.7 V
0.8 V
0.2
0.25
1.1 V
0.3
0.4
0.45
0.6
5
V
OL
V
= 5 mA
1.4 V
= 8 mA
1.65 V
2.3 V
= 9 mA
I
I
I
A or B inputs
V = V
CC
or GND
0 to 2.7 V
0
µA
µA
µA
pF
I
I
V or V = 2.7 V
10
off
I
O
V = V
or GND,
or GND
I = 0
O
0.8 V to 2.7 V
2.5 V
10
CC
I
CC
C
V = V
2.5
i
I
CC
†
All typical values are at T = 25°C.
A
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉ ꢇ
ꢊ ꢅꢄꢋ ꢇ ꢌꢍ ꢁꢎ ꢅꢏ ꢎ ꢐꢀ ꢍ ꢏꢍ ꢑ ꢒꢌ ꢐꢓ ꢈ ꢄꢏꢒ
SCES478A − AUGUST 2003 − REVISED NOVEMBER 2003
switching characteristics over recommended operating free-air temperature range, C = 15 pF
L
(unless otherwise noted) (see Figure 1)
V
= 1.2 V
0.1 V
V
= 1.5 V
0.1 V
V
= 1.8 V
V
= 2.5 V
0.2 V
CC
CC
CC
0.15 V
CC
V
= 0.8 V
CC
TYP
7.5
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
0.7 3.3
MIN MAX
0.6 1.9
MIN TYP MAX
0.5 1.5
MIN MAX
0.4 1.1
t
pd
A or B
1
ns
Y
switching characteristics over recommended operating free-air temperature range, C = 30 pF
L
(unless otherwise noted) (see Figure 1)
V
= 1.8 V
V
= 2.5 V
CC
CC
0.2 V
FROM
(INPUT)
TO
(OUTPUT)
0.15 V
TYP
1.6
PARAMETER
UNIT
MIN
MAX
MIN
MAX
t
pd
A or B
1.2
2.1
1
1.7
ns
Y
operating characteristics, T = 25°C
A
V
= 0.8 V
CC
TYP
V
= 1.2 V
CC
TYP
V
CC
= 1.5 V
V
CC
= 1.8 V
V
CC
= 2.5 V
TEST
PARAMETER
UNIT
CONDITIONS
TYP
TYP
TYP
Power dissipation
capacitance
C
f = 10 MHz
13
13
13
13
14
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢇ
ꢊꢅꢄ ꢋ ꢇ ꢌꢍꢁ ꢎꢅꢏ ꢎꢐ ꢀꢍ ꢏ ꢍꢑꢒꢌ ꢐ ꢓ ꢈ ꢄꢏꢒ
SCES478A − AUGUST 2003 − REVISED NOVEMBER 2003
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
S1
S1
Open
R
L
t
t
/t
Open
From Output
Under Test
PLH PHL
GND
t
/t
2 × V
CC
GND
PLZ PZL
/t
PHZ PZH
C
L
R
L
(see Note A)
V
∆
C
L
R
V
CC
L
0.8 V
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
0.1 V
0.1 V
15 pF
1.2 V 0.1 V
1.5 V 0.1 V
1.8 V 0.15 V
2.5 V 0.2 V
1.8 V 0.15 V
2.5 V 0.2 V
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
LOAD CIRCUIT
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
V
CC
Timing Input
V
CC
/2
0 V
t
w
t
t
h
su
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
V
CC
/2
V
CC
/2
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
Input
0 V
0 V
t
t
t
t
t
PHL
/2
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
V
V
V
OH
CC
V
/2
/2
V
V
/2
/2
V
CC
Output
CC
CC
S1 at 2 × V
(see Note B)
V
V
CC
OL
∆
OL
OL
t
t
t
PLH
/2
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
− V
OH
∆
V
CC
V
CC
CC
Output
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, slew rate ≥ 1 V/ns.
O
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
are the same as t
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,13
0,65
8
5
0,15 NOM
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
0,25
1
4
0° – 8°
0,60
0,20
3,15
2,75
1,30 MAX
Seating Plane
0,10
0,10
0,00
4188781/C 09/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
相关型号：
SN74AUC2G34
Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
TI
SN74AUC2G34DBVR
Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
TI
SN74AUC2G34DBVRE4
Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
TI
©2020 ICPDF网 联系我们和版权申明