SN74AUC2G66DCTRG4 [TI]
DUAL 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO8, GREEN, PLASTIC, SSOP-8;
| 型号： | SN74AUC2G66DCTRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO8, GREEN, PLASTIC, SSOP-8 光电二极管 |
| 文件： | 总21页 (文件大小：873K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A–NOVEMBER 2003–REVISED JANUARY 2007
FEATURES
DCT OR DCU PACKAGE
(TOP VIEW)
•
Available in the Texas Instruments
NanoFree™ Package
1A
1B
2C
V
CC
1
2
3
4
8
7
6
5
•
•
•
•
•
•
•
Operates at 0.8 V to 2.7 V
Sub-1-V Operable
1C
2B
2A
Max tpd of 0.5 ns at 1.8 V
GND
Low Power Consumption, 10 µA at 2.7 V
High On-Off Output Voltage Ratio
High Degree of Linearity
YZP PACKAGE
(BOTTOM VIEW)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
4
3
2
1
5
6
7
8
GND
2C
2A
2B
1C
V
•
ESD Performance Tested Per JESD 22
1B
1A
–
2000-V Human-Body Model
(A114-B, Class II)
CC
–
–
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This dual analog switch is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.1-V to 2.7-V VCC
operation.
The SN74AUC2G66 can handle both analog and digital signals. It permits signals with amplitudes of up to 2.7-V
(peak) to be transmitted in either direction.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SSOP – DCT
Reel of 3000
SN74AUC2G66YZPR
_ _ _U6_
–40°C to 85°C
Reel of 3000
Reel of 3000
SN74AUC2G66DCTR
SN74AUC2G66DCUR
U66_ _ _
U66_
VSSOP – DCU
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
CONTROL
INPUT
(C)
SWITCH
L
OFF
ON
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A–NOVEMBER 2003–REVISED JANUARY 2007
LOGIC DIAGRAM (POSITIVE LOGIC)
1
4
2
B
A
C
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
MAX
3.6
3.6
UNIT
VCC
VI
Supply voltage range(2)
Input voltage range(2)(3)
Switch I/O voltage range
V
V
(2)(3)
VI/O
IIK
–0.5 VCC + 0.5
V
Control input clamp current
I/O port diode current
VI < 0
–50
±50
mA
mA
mA
mA
IIOK
IT
VI/O < 0 or VI/O > VCC
VI/O = 0 to VCC
On-state switch current
±50
Continuous current through VCC or GND
±100
220
227
102
DCT package
DCU package
YZP package
θJA
Package thermal impedance(4)
°C/W
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground unless otherwise specified.
(3) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A–NOVEMBER 2003–REVISED JANUARY 2007
Recommended Operating Conditions(1)
MIN
0.8
MAX UNIT
VCC
Supply voltage
2.7
V
VCC = 0.8 V
VCC
VIH
High-level input voltage
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
0.65 × VCC
1.7
V
0
VIL
Low-level input voltage
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.35 × VCC
V
0.7
VCC
3.6
20
VI/O
VI
I/O port voltage
0
0
V
V
Control input voltage
VCC = 0.8 V to 1.65 V(2)
VCC = 1.65 V to 2.3 V(3)
VCC = 2.3 V to 2.7 V(3)
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
20
ns/V
20
TA
–40
85
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) The data was taken at CL = 15 pF, RL = 2 kΩ (see Figure 1).
(3) The data was taken at CL = 30 pF, RL = 500 Ω (see Figure 1).
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.1 V
1.65 V
2.3 V
1.1 V
1.65 V
2.3 V
1.1 V
1.65 V
2.3 V
MIN TYP(1)
MAX UNIT
17
7
40
VI = VCC or GND,
IS = 4 mA
IS = 8 mA
IS = 4 mA
IS = 8 mA
IS = 4 mA
IS = 8 mA
ron
On-state switch resistance
VC = VIH
20
15
180
80
20
3
Ω
Ω
Ω
(see Figure 1 and Figure 2)
4
131
32
15
VI = VCC to GND,
VC = VIH
ron(p)
Peak on resistance
(see Figure 1 and Figure 2)
Difference of
on-state resistance
between switches
VI = VCC to GND,
VC = VIH
∆ron
1
(see Figure 1 and Figure 2)
1
VI = VCC and VO = GND, or
±1
IS(off)
Off-state switch leakage current
On-state switch leakage current
VI = GND and VO = VCC
VC = VIL (see Figure 3)
,
2.7 V
2.7 V
µA
µA
±0.1(2)
±1
±0.1(2)
±5
VI = VCC or GND, VC = VIH, VO = Open
(see Figure 4)
IS(on)
II
Control input current
VI = VCC or GND
0 to 2.7 V
0.8 V to 2.7 V
2.5 V
µA
µA
pF
pF
pF
ICC
Supply current
VI = VCC or GND,
IO = 0
10
Cic
Control input capacitance
Switch input/output capacitance
Switch input/output capacitance
2.5
3
Cio(off)
Cio(on)
2.5 V
2.5 V
7
(1) ta = 25°C
(2) The data was taken at CL = 15 pF, RL = 2 kΩ (see Figure 1).
3
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SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A–NOVEMBER 2003–REVISED JANUARY 2007
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 5)
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 0.8 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
1
MIN MAX
MIN MAX MIN TYP MAX
MIN
MAX
(1)
tpd
A or B
B or A
A or B
A or B
0.6
0.5
2.1
3
0.5
1.6
3.3
0.4
1.4
2.7
ns
ns
ns
ten
C
C
5
0.5
0.5
3
4
0.5
0.5
0.5
0.5
0.9
2.6
0.5
0.5
tdis
5.3
(1) The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load
capacitance when driven by an ideal voltage source (zero output impedance).
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 5)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN TYP MAX
MIN
MAX
(1)
tpd
A or B
B or A
A or B
A or B
0.7
0.7
2.3
2
ns
ns
ns
ten
C
C
0.5
0.5
1.6
2.7
2.7
3.4
0.5
0.5
tdis
(1) The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load
capacitance when driven by an ideal voltage source (zero output impedance).
Analog Switch Characteristics
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
VCC
TYP UNIT
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
101
150
175
250
CL = 50 pF, RL = 600 Ω,
fin = sine wave
(see Figure 6)
400
MHz
450
Frequency response
(switch ON)
A or B
B or A
>500
>500
>500
>500
–60
CL = 5 pF, RL = 50 Ω,
fin = sine wave
(see Figure 6)
–60
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 7)
–60
–60
–60
dB
Crosstalk
(between switches)
A or B
B or A
–65
–65
–65
–65
–65
CL = 5 pF, RL = 50 Ω,
fin = 1 MHz (sine wave)
(see Figure 7)
4
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SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A–NOVEMBER 2003–REVISED JANUARY 2007
Analog Switch Characteristics (continued)
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
VCC
TYP UNIT
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
0.8 V
1.1 V
1.4 V
1.65 V
2.3 V
9
14
Crosstalk
(control input to signal
output)
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (square wave)
(see Figure 8)
C
A or B
15
16
mV
20
–50
–50
–50
–50
–50
–60
–60
–60
–60
–60
7
CL = 50 pF, RL = 600 Ω,
fin = 1 MHz (sine wave)
(see Figure 9)
Feedthrough attenuation
(switch OFF)
A or B
B or A
dB
CL = 5 pF, RL = 50 Ω,
fin = 1 MHz (sine wave)
(see Figure 9)
0.256
0.04
0.03
0.01
3.7
CL = 50 pF, RL = 10 kΩ,
fin = 1 kHz (sine wave)
(see Figure 10)
A or B
B or A
Sine-wave distortion
%
0.4
CL = 50 pF, RL = 10 kΩ,
fin = 10 kHz (sine wave)
(see Figure 10)
A or B
B or A
0.04
0.02
0.02
Operating Characteristics
TA = 25°C
VCC = 0.8 V
VCC = 1.2 V
VCC = 1.5 V
TYP
VCC = 1.8 V
VCC = 2.5 V
TYP
TEST
CONDITIONS
PARAMETER
UNIT
TYP
TYP
TYP
Power dissipation
capacitance
Cpd
f = 10 MHz
2.5
2.5
2.5
2.5
2.5
pF
5
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SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A–NOVEMBER 2003–REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
V
CC
V
CC
B or A
A or B
V = V or GND
V
I
CC
O
C
V
IH
V
C
(ON)
GND
I
S
VI * VO
W
ron
+
IS
V
V – V
I
O
Figure 1. On-State Resistance Test Circuit
120
100
V
CC
= 1.1 V
80
60
40
V
CC
= 1.65 V
20
0
V
CC
= 2.3 V
0
1
2
3
Figure 2. Typical ron as a Function of Voltage (VI) for VI = 0 to VCC
6
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SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A–NOVEMBER 2003–REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
V
CC
V
CC
B or A
A or B
V
I
A
V
V
O
C
IL
V
C
(OFF)
GND
Condition 1: V = GND, V = V
CC
I
O
Condition 2: V = V , V = GND
I
CC
O
Figure 3. Off-State Switch Leakage-Current Test Circuit
V
CC
CC
V
B or A
A or B
A
V = V or GND
V
O
I
CC
V
O
= Open
C
V
IH
V
C
(ON)
GND
Figure 4. On-State Leakage-Current Test Circuit
7
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SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A–NOVEMBER 2003–REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
t /t
r f
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
0.8 V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
≤2 ns
≤2 ns
≤2 ns
≤2 ns
≤2 ns
≤2 ns
≤2 ns
V
/2
CC
/2
CC
/2
CC
/2
CC
/2
CC
/2
CC
/2
CC
2 × V
2 × V
2 × V
2 × V
2 × V
2 × V
2 × V
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
0.1 V
0.1 V
0.1 V
CC
CC
CC
CC
CC
CC
CC
1.2 V ± 0.1 V
1.5 V ± 0.1 V
V
V
V
V
V
V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
0.15 V
0.15 V
0.15 V
0.15 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
OL
+ V
∆
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
− V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, slew rate ≥ 1 V/ns.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
8
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SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A–NOVEMBER 2003–REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
V
CC
CC
V
0.1 µF
B or A
A or B
C
V
O
R
L
C
L
V
IH
50 Ω
f
in
V
C
(ON)
GND
V /2
CC
R /C : 600 Ω / 50 pF
L
L
R /C : 50 Ω / 5 pF
L
L
Figure 6. Frequency Response (Switch ON)
V
CC
CC
V
0.1 µF
50 Ω
1B or 1A
1A or 1B
V
O1
R
600 Ω
in
C
R
600 Ω
L
L
C
V
IH
50 pF
V
C
f
in
(On)
V /2
CC
2B or 2A
2A or 2B
V
O2
R
600 Ω
C
L
50 pF
L
C
R
600 Ω
in
V
IL
V
C
(Off)
GND
V /2
CC
20log (V /V ) or
10 O2 I1
20log (V /V )
10 O1 I2
Figure 7. Crosstalk (Between Switches)
9
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SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A–NOVEMBER 2003–REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
V
CC
V
CC
R
in
600 Ω
B or A
A or B
C
V /2
CC
V
O
R
L
C
L
600 Ω
50 pF
V
C
GND
V /2
CC
50 Ω
Figure 8. Crosstalk (Control Input – Switch Output)
V
CC
CC
V
0.1 µF
B or A
A or B
C
V
O
C
L
R
L
R
L
V
IL
50 Ω
V
C
f
in
(OFF)
GND
V /2
CC
V /2
CC
R /C : 600 Ω / 50 pF
L
L
R /C : 50 Ω / 5 pF
L
L
Figure 9. Feedthrough, Switch Off
10
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SN74AUC2G66
DUAL BILATERAL ANALOG SWITCH
www.ti.com
SCES507A–NOVEMBER 2003–REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
V
CC
CC
V
10 µF
10 µF
B or A
A or B
C
V
O
C
L
R
10 kΩ
L
V
IH
50 pF
600 Ω
V
C
f
in
(ON)
GND
V /2
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0.8 V, V = 0.7 V
I
P-P
= 1.1 V, V = 1 V
I
P-P
= 1.4 V, V = 1.2 V
I
P-P
= 1.65 V, V = 1.4 V
I
P-P
P-P
= 2.3 V, V = 2 V
I
Figure 10. Sine-Wave Distortion
11
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
SN74AUC2G66DCTR
SN74AUC2G66DCTRE4
SN74AUC2G66DCTRG4
SN74AUC2G66DCUR
SN74AUC2G66DCURE4
SN74AUC2G66DCURG4
SN74AUC2G66YZPR
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SM8
SM8
DCT
8
8
8
8
8
8
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
U66
Z
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DCT
DCT
DCU
DCU
DCU
YZP
3000
3000
3000
3000
3000
3000
Green (RoHS
& no Sb/Br)
U66
Z
SM8
Green (RoHS
& no Sb/Br)
U66
Z
US8
Green (RoHS
& no Sb/Br)
(66 ~ U66R)
(UR ~ UZ)
US8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
SNAGCU
U66R
U66R
U67
US8
Green (RoHS
& no Sb/Br)
DSBGA
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AUC2G66DCUR
SN74AUC2G66DCURG4
SN74AUC2G66YZPR
US8
US8
DCU
DCU
YZP
8
8
8
3000
3000
3000
180.0
180.0
180.0
8.4
8.4
8.4
2.25
2.25
1.02
3.35
3.35
2.02
1.05
1.05
0.63
4.0
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q1
DSBGA
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74AUC2G66DCUR
SN74AUC2G66DCURG4
SN74AUC2G66YZPR
US8
US8
DCU
DCU
YZP
8
8
8
3000
3000
3000
202.0
202.0
220.0
201.0
201.0
220.0
28.0
28.0
34.0
DSBGA
Pack Materials-Page 2
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,13
0,65
8
5
0,15 NOM
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
0,25
1
4
0° – 8°
0,60
0,20
3,15
2,75
1,30 MAX
Seating Plane
0,10
0,10
0,00
4188781/C 09/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D: Max = 1.918 mm, Min =1.858 mm
E: Max = 0.918 mm, Min =0.858 mm
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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